AD6652BBC datasheet(59/76 Pages) AD

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AD6652

Rev. 0 | Page 59 of 76

the SYNC occurs. If this bit is high, then the phase

not updated to the

working register until the channel is either brought out of sleep

es a value of 1. If the frequency

as the shadow is written.

Memory Map

Bit Wid

NCO control register at Channel Address 0x88. When this bit is

low, then the phase accumulator of the NCO is not cleared, but

starts to add the new NCO frequency word to the accumulator

as soon as

accumulator of the NCO is cleared to 0, and the new word is

then accumulated.

0x85: NCO Frequency Register 0

This register represents the 16 LSBs of the NCO frequency

word. These bits are shadowed and are

mode, or a Soft_SYNC or Pin_SYNC has been issued. In the

latter two cases, the register is updated when the frequency

Table 24. Channel Address

hold-off counter count reach

hold-off counter value is set to a value of 1, then the register is

updated as soon as the shadow is written.

0x86: NCO Frequency Register 1

This register represents the 16 MSBs of the NCO frequency

word. These bits are shadowed and are not updated to the

working register until the channel is either brought out of sleep

mode, or a Soft_SYNC or Pin_SYNC has been issued. In the

latter two cases, the register is updated only when the frequen

hold-off counter count reaches a value of 1. If the frequency

hold-off counter is set to a value of 1, then the register is

updated as soon

Channel Address

Comments

00–7F

Coefficient Memory (CMEM)

128 x 20-bit memory

CHANNEL SLEEP

Sleep bit from EXT_ADDRESS 3

Soft_Sync Control Register

Hop

Start

Pin_SYNC Control Register

First SYNC only

Hop_En

Start_En

Start Hold-Off Counter

Start hold-off value

NCO Frequency Hold-Off Counter

NCO_FREQ hold-off value

NCO Frequency Register 0

NCO_FREQ[15:0]

NCO Frequency Register 1

NCO_FREQ[31:16]

NCO Phase Offset Register

NCO_PHASE[15:0]

NCO Control Register

[1:0]

8-7:

SYNC input select

00 = A, 01 = B, 10 = C, 11 = D

Input port select B or A, 0 = A, 1 = B

5-4:

Reserved, write both bits logic low

Clear phase accumulator on hop

Amplitude dither

Phase dither

Bypass (A-input -> I-path, B -> Q)

89–8F

Unused

rCIC2 Decimation − 1

MrCIC2 − 1

rCIC2 Interpolation − 1

LrCIC2 − 1

rCIC2 Scale

11:

Reserved, write to logic low

10:

Reserved, write to logic low

:0]

9-5:

rCIC2 _QUIET [4

4-0:

rCIC2_LOUD [4:0]

Reserved

d (must be written low)

Reserve

CIC5 Decimation − 1

MCIC5 − 1

CIC5 Scale

4-0:

CIC5_SCALE[4:0]

Reserved

Reserved (must be written low)

97–9F

Unused

RCF Decimation − 1

MRCF − 1

RCF Decimation Phase

PRCF

RCF Number of Taps − 1

NTaps − 1

RCF Coefficient Offset

CORCF

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