AD6652BBC datasheet(69/76 Pages) AD

69 / 76 page

AD6652

Rev. 0 | Page 69 of 76

irst sync high is recognized and

ed. If this register is written to 0, the

onized.

sync

DDC processing Channel 2. Therefore, if the user

intends to use AGC A’s hold-off counter, the user must either

ed to

desired delay before a new CIC

per

gger-

e every time the pin is written high.

This 8-bit register contains the desired output power level or

ng on the mode of operation.

t R level can be set from 0 dB to −23.99 dB

binary floating-point representa-

by the 6-bit man-

and the exponent is in

0101 represents 2 × 6.02 + 37 ×

0.094 = 15.518 dB.

e initial value for a signal gain used

12-bit value sets the initial signal

dB in steps of 0.024 dB. A 12-bit

inary floating-point representation is used with a 4-bit expo-

nent followed by the 8-bit mantissa. For example:

0111’10001001 represents 7 × 6.02 + 137 × 0.024 = 45.428 dB.

x16: AGC B Loop Gain

his 8-bit register is used to define the open loop gain K. Its

value can be set from 0 to 0.996 in steps of 0.0039. This value of

K is updated in the AGC loop each time the AGC is initialized.

0x17: AGC B Pole Location

This 8-bit register is used to define the open loop filter pole

location P. Its value can be set from 0 to 0.996 in steps of 0.0039.

This value of P is updated in the AGC loop each time the AGC

is initialized. This open loop pole location directly impacts the

closed loop pole locations as explained in the Automatic Gain

Control section.

amples

tio from 1 to

4096. Set an appropriate scaling factor to avoid loss of bits.

put through either a parallel port interface or a link

ace. When 0x1B, Bit 7 = 0, the use of Link Port A is

Ps or

on Parallel Port A. When

Bit 0 = 0, Parallel Port A outputs data from the RCF according

by Bits 1–4. When Bit 0 = 1, Parallel

according to the format

it 1 determines if Parallel Port A

Bit 2 determines if Parallel Port A

. The order of output depends on

the rate of triggers from each AGC, which in turn is determined

by the decimation rate of the channels feeding it. In channel

ine which combination of

ut. The output order

ived from each channel,

tion rate of each channel.

be used to determine

Bit 5 determines the format of the output data words. When

Bit 5 = 0, Parallel Port A outputs 16-bit words on its 16-bit bus.

This means that I and Q data are interleaved, and the IQ

indicator pin determines whether data on the port is I data or

Q data. When Bit 5 = 1, Parallel Port A is outputting an 8-bit

I word and an 8-bit Q word at the same time, and the IQ

indicator pins are high.

0x1B: Link Port Control A

Data is output through either a parallel port interface or a link

port interface. The link port provides an efficient data link

between the AD6652 and a TigerSHARC DSP and can be

enabled by setting 0x1D, Bit 7 = 1.

If this bit is set, only the f

succeeding sync events are ignored until Bit 1 is reset.

Bit 0 is used to bypass the AGC section, when it is set. When the

AGC is bypassed, the output data is the 16 MSBs of the 24-bit

input data from the half-band filter.

0x13: AGC B Hold-Off Counter

The AGC B hold-off counter is loaded with the 16-bit value

written to this address when Sync Now is written high or a

Pin_Sync signal is receiv

AGC cannot be synchr

Note: The

ssigned to

hold-off counter of AGC B shares the pin

attach the external sync signal to the pin sync that is assign

DDC Channel 2, or use the software-controlled sync now

function of Bit 3 at 0x12.

rogrammed with a 16-bit

The hold-off counter must be p

er that corresponds to the

numb

decimated value is updated. Writing a logic high to the pro

pin sync pin triggers the AGC hold-off counter with a retri

able one-shot puls

0x14: AGC B Desired Level

desired clipping level, dependi

This desired reques

in steps of 0.094 dB. An 8-bit

tion is used with a 2-bit exponent followed

eps of 0.094 dB

tissa. The mantissa is in st

6.02 dB steps. For example: 10’10

0x15: AGC B Signal Gain

This register is used to set t

This

in the gain multiplier.

ain between 0 dB and 96.296

0x18: AGC B Average S

This 6-bit register contains the scale used for the CIC filter and

the number of power samples to be averaged before being fed to

the CIC filter.

Bits 5–2 define the scale used for the CIC filter.

Bits 1–0 define the number of samples to be averaged before

they are sent to the CIC decimating filter. This number can be

set between 1 and 4 with bit representation 00 meaning one

sample and bit representation 11 meaning four samples.

0x19: AGC B Update Decimation

This 12-bit register sets the AGC decimation ra

0x1A: Parallel Port Control A

Data is out

t interf

por

disabled and the use of Parallel Port A is enabled. The parallel

port provides different data modes for interfacing with DS

FPGAs.

Bit 0 selects which data is output

to the format specified

Port A outputs the data from the AGCs

specified by Bits 1 and 2

In AGC mode, Bit 0 = 1 and B

rom AGC A.

can output data f

can output data from AGC B

mode, Bit 0 = 0 and Bits 1–4 determ

utp

the four processing channels is o

depends on the rate of triggers rece

which is determined by the decim

The channel output indicator pins can

which data came from which channel.

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