AD6652BBC datasheet(54/76 Pages) AD

54 / 76 page

AD6652

Rev. 0 | Page 54 of 76

ission is a 4-bit

the link port control registers (0x1B and

and the

out of

The length of the wait before data transm

programmable value in

0x1D Bits 6–3). This value allows the AD6652 PCLK

TigerSHARC PCLK to be run at different rates and

phase.

⎟

⎠

⎞

⎜

⎝

⎛

≥

TSHARC

LCLK

ciel

WAIT

6652

WAIT ensures that the amount of time the AD6652 needs to

wait to begin data transmission is at least equal to the minimum

amount of time the TigerSHARC is expecting it to wait. If the

PCLK of the AD6652 is out of phase with the PCLK of the

TigerSHARC and the argument to the ceil() function is an

integer, then WAIT must be strictly greater than the value given

in the above formula.

If the LCLKs are in phase, then the maximum output data rate

TSHARC

LCLK

6652

15 ×

≤

Otherwise, it is

TSHARC

LCLK

6652

14 ×

≤

TIGERSHARC CONFIGURATION

Because the AD6652 is always the transmitter in this link and

the TigerSHARC is always the receiver, the following values can

be programmed into the LCTL register for the link port used t

receive AD6652 output data.

Table 21. TigerSHARC LCTLx Register Configuration

Value

VERE

SPD

User1

LTEN

PSIZE

TTOE

CERE

LREN

RTOE

1 The term User means that the actual register value depends on the user’s

application.

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