AD6652BBC datasheet(32/76 Pages) AD

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AD6652

Rev. 0 | Page 32 of 76

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wer

input signal goes above the upper threshold, the appropriate LI

signal becomes a ive. Once the signal falls below the lower

threshold, the counter begins counting. If the input condition

goes above the lower threshold, the counter is reset and starts

the input condition falls below the lower progra

threshold.

To provide hysteresis, a dwell time register (see Table 28) is

available to hold off switching of the control line for a

predetermined number of clocks. Once the input condition is

below the lower threshold, the programmable counter begins

counting high speed clocks. As long as the input signal stays

below the lower threshold for the number of high speed clock

cycles programmed, the attenuator is removed on the terminal

count. However, if the input condition goes above the lo

threshold with the counter running, it is reset and must fall

below the lower threshold again to initiate the process. This

prevents unnecessary switching between states.

Threshold settings for LI are illustrated in Figure 47. When the

again, as shown in the figure. Once the counter has terminated

to 0, the LI line goes inactive.

HIGH

DWELL TIME

LOW

UPPER

THRESHOLD

LOWER

THRESHOLD

COUNTER

RESTARTS

TIME

Figure 47. Threshold Settings for LI

The LI line can be used for a variety of functions. It can be used

to set the controls of an attenuator, DVGA, or integrated and

used with an analog VGA. To simplify the use of this feature, the

cludes two separate gain settings, one when this line

e (rCIC2_QUIET[4:0] stored in Bits 9:5 of 0x92

active (rCIC2_LOUD[4:0] stored

and external attenuator gain (if used). If no external

attenuator is used, both the rCIC2_QUIET and rCIC2_LOUD

o minimize loop delays. Any of the four

tains a correct scale value

throughout the process, making it totally independent. The

AD6652 includes a programmable pipeline delay that can be

used to compensate for the inherent 7-clock pipeline delay

associated with the front-end ADC. This feature promotes

smoother switching among gain settings.

AD6652 in

is inactiv

in Bits 4:0 of 0x92 r ister). This allows the digital gain to

adjusted to the external changes. In conjunction with the gain

setting, a variable hold-off is included to compensate for the

pipeline delay of the ADC and the switching time of the gain

control element. Together, these two features provide seamless

gain switching.

rCIC2_LOUD[4:0] and rCIC2_QUIET[4:0]

These 5-bit registers contain scale values to compensate for th

rCIC2 gain

registers contain the same value. These 5-bit scale values are

stored in the rCIC2 scale register (0x92) and the scaling is

applied before the data enters the rCIC2 resampling filter.

Both DDC input ports of the AD6652 have independent ga

control circuits, allowing each respective LI pin to be pro-

grammed to different set points. Note that the input gain

control circuits are wideband and are implemented prior to any

filtering elements t

DDC processing channels can be set to monitor either of the

DDC input ports.

The chip also provides appropriate scaling of the internal data,

based on the attenuation associated with the LI signal. In thi

manner, data to the DSP main

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