AD6652BBC datasheet(64/76 Pages) AD

64 / 76 page

AD6652

Rev. 0 | Page 64 of 76

Table 28. M

p for Input Port Control Registers

Wid

mments

emory Ma

Channel Addre

Bit

Lower Threshold A

Lower threshold for Input A

9–0:

Upper Threshold A

Upper threshold for Input A

9–0:

Dwell Time A

19–0:

Minimum time below Lower Threshold A

Gain Range A Control

ister

Output polarity LIA and LIA

Reg

(0) Reserved

2–0:

Linearization hold-off register

Lower Threshold B

Lower threshold for Input B

9–0:

Upper Threshold B

Upper threshold for Input B

9–0:

Dwell Time B

19–0:

Minimum time below Lower Threshold B

Gain Range B Control Register

ity LIB and LIB

Output polar

(0) Reserved

2–0:

Linearization hold-off register

OUTPUT PORT CONTROL REGISTERS

roup o registers is dedicated to data management af

dual channels have processed the incoming data. The

nage data nterleaving, 2× interpolation, A C functions,

t port

signment, and output port setu . Because the

re two outp t ports, A and B, the data must e funneled fr

ur channe down to two. These registers a

onsible for

g the

ta directly to the proper outpu

ort(s) or

uring th

ther post-filteri

tages (AG

nd so on) before the output port is selected

o access th output port registers for Outpu

orts A and , Bit

f Externa

ddress 3 (the sleep register) m st be written logic

h. The ch nnel address register (CAR) is t en written wi

e address t the correct output port registe

ee Table 29 for a

mplete lis

g and brief description of all r isters.

0x07: Reserved

erved. Al

its should be written logic low

8: LHB

he acronym for interpolating half-band, with L bei

ly accep d symbol for interpolation. This register incl des

e interleaving stage as well as the half-band filter stage, as

own in Fi

e 64. These two stages are con olled separa

om the fin AGC stage, so that they do no

et lost amon

merous A C control elements.

it 3, the LHB A enable bit, acts as an on/off

tch for the

terleave st e, half-band filter, and the AGC stage. See

igure 64. If it 3 is low, the interleave stage is shut down a

ents any

ation of data to t

maining

ages. This condition is desirable when the t ree stages are

eeded and ower conservation is desired. W en Bit 3 is h

e interleav

tage is active and works to int

eave the dat of

p to four D C channels according to the tr th table of Bi 2

nd Bit 1. The data is then propagated to the LHB and AGC

ages with bypass opportunities included.

h channels are interleaved. The truth

for these bits is shown in Table 29.

when high, directs data from the interleave

alf-band filter stage and proceed directly to

tage without interpolation. The channel data streams

ey are not filtered or interpolated. The

onfiguration is two times the

When Bit 0 is low, data from the interleave stage is passed

the half-band filter and undergoes a 2× interpolation

t data rate of the half-band is four

wo channels can be inter-

annels are selected using only Bit 1; Bit 2 is the LHB B

0x0A: AGC A Control Register

utput word length of the AGC. The output

12, or 16 bits wide. The truth table to

ord lengths is given in the Table 29

of this register sets the mode of operation for the AGC.

he AGC tracks to maintain the output signal

s 1, the AGC tracks to maintain a constant

rror. See the Automatic Gain Control section for

odes.

sed to configure the synchronization of the AGC.

The CIC decimator filter in the AGC can be directly synchro-

xternally generated signal. When synchronized, the

ple for the AGC error calculation

y, the AGC gain changes can be synchro-

nized to a Rake receiver.

This g

ter

indivi

outpu

re resp

guidin

t p

deto

e data through o

ng s

t P

5 o

l A

hig

r. S

tin

0x00–

Res

l b

0x0

A Control Registe

LHB is t

ng a

wide

gur

tely

t g

g th

swi

further propag

he re

not

igh,

e s

erl

its 2 and 1 choose whic

table

Bit 0, the bypass bit,

stage to bypass the h

the AGC s

re still interleaved, but th

aximum data rate from this c

chip rate.

through

ate. The maximum outpu

mes the chip rate.

0x09: LHB B Control Register

ame as LHB A, except that only t

leaved. Ch

nable bit.

Bits 7–5 define the o

word can be 4 to 8, 10,

btain different output w

emory map, 0x0A.

Bit 4

When this bit is 0, t

level; when this bit i

clipping e

etails about these two m

Bits 3–1 are u

nized to an e

GC outputs an update sam

nd filtering. This wa

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