AD6652BBC datasheet(28/76 Pages) AD

28 / 76 page

AD6652

Rev. 0 | Page 28 of 76

with a nominal 50% duty cycle. Duty cycle

affec

crea

sam

low

the

quire and lock to the new rate.

the c

inpu

fINPUT) due only to aperture jitter (tA) can be

In the equation, the rms aperture jitter, t , represents the root-

signal with digital noise. Low jitter,

nal

last s

e power dissip

d by the AD6652 front-end AD is propor-

nal to its samp

g rate. Norma

DC operation

uires that

th PDWN pin

e set to logic lo

he ADC can

placed in

ower-down m

e by setting bo

PDWN pins t

gic high.

w power dissi

ion in power-d

n mode is ach

ed by

tting down th

eference buffers and biasing ne

rks of

th ADC chann

. Both power-

pins must b

riven

ether either h

or low for pro r ADC operat

r maximum p

er savings, the

LK and analo

put(s)

ould remain st

while in stan

mode, result

in a

ical power co

ption of 1 m

for the ADC.

he clock

uts remain ac

while in stan

mode, typical power

nsumption for

e ADC is 12 mW

ADC Wake-Up Time

upling capacitors on REFT and REFB are discharged

de, and then must be recharged when

the

upling capacitors on REFT

and

y discharge the

e buffer decoupling capacitors, and 5 ms to restore full

Clock Input Considerations

Typical high speed ADCs use both clock edges to generate a

modulating the clock

crystal-controlled osci

variety of internal timing signals, and as a result can be sensiti

to ACLK clock duty cycle. Commonly a 5% tolerance is

required on the clock duty cycle to maintain dynamic perform-

ance characteristics. The AD6652 contains a clock duty cycle

stabilizer that re-times the nonsampling edge, providing a

internal clock signal

sta ilizing is engaged by setting DUTYEN to logic high. This

allo s a wide range of ACLK clock input duty cycles without

ting the performance of the AD6652 ADC stage.

Th duty cycle stabilizer uses a delay-locked loop (DLL) to

te the nonsampling edge. As a result, any changes to the

pling frequency require approximately 2 ms to 3 ms to al

DLL to ac

speed, high resolution ADCs are sensitive to the quality of

lock input. The degradation in SNR at a given full-scale

t frequency (

calculated with the following equation:

SNR degradation = 20 × log10 [1/2 × p × fINPUT × tA]

sum square of all jitter sources, which include the clock inpu

analog input signal, and ADC aperture jitter specification.

Undersampling applications are particularly sensitive to jitter.

To minimize clock jitter, treat the ACLK clock input as an

analog signal. Power supplies for clock drivers should be

separated from the ADC output driver supplies to avoid

llators make the best clock sources. If the

ACLK clock is generated from another type of source (by

gating, dividing, or other methods), re-time it by the origi

clock at the

tep.

ADC Power-Down Mode

ate

tio

lin

l A

req

s b

w. T

a p

o lo

pat

iev

shu

e r

two

els

down

e d

tog

igh

ion

g in

atic

dby

ing

typ

nsum

If t

inp

tive

dby

The deco

when entering standby mo

returning to normal operation. As a result, the wake-up time is

related to the time spent in standby mode. Shorter standby

cycles result in proportionally shorter wake-up times. With

recommended 0.1 µF and 10 µF deco

REFB, it takes approximately 1 s to full

referenc

operatio

AD6652BBC 数据表(PDF) 28 Page - Analog Devices

AD6652BBC 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载