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AD6652BBC 数据表(PDF) 1 Page - Analog Devices

部件名 AD6652BBC
功能描述  12-Bit, 65 MSPS IF to Baseband Diversity Receiver
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6652BBC 数据表(HTML) 1 Page - Analog Devices

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12-Bit, 65 MSPS
IF to Baseband Diversity Receiver
AD6652
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 90 dB in 150 kHz bandwidth (to Nyquist
@ 61.44 MSPS)
Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
Integrated dual-channel ADC:
Sample rates up to 65 MSPS
IF sampling frequencies to 200 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range (1 V to 2 V p-p)
Differential analog inputs
ADC clock duty cycle stabilizer
85 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC):
Crossbar switched DDC inputs
Digital resampling for noninteger decimation
Programmable decimating FIR filters
Flexible control for multicarrier and phased array
Dual AGC stages for output level control
Dual 16-bit parallel or 8-bit link output ports
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,
IS95, IS136, CDMA2000, IMT-2000
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM
/
/
12
12
CHANNEL A
CHANNEL B
LIA
LIA
LIB
LIB
OTRA
OTRB
PSEUDO
RANDOM
NOISE
SEQUENCE
SYNCA
SYNCB
SYNCC
SYNCD
ACLK
VINA+
VINA–
VINB+
VINB–
VREF
SENSE
REFTA
REFBA
REFTB
REFBB
PDWN
SHRDREF
DUTYEN
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
RCF OUTPUTS
CHANNELS 0, 1, 2, 3
TO OUTPUT PORTS
TO OUTPUT PORTS
TO OUTPUT PORTS
TO OUTPUT
PORTS
DUAL-CHANNEL 12-BIT A/D FRONT END
WIDEBAND DIGITAL DOWNCONVERTER (DDC)
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
+3.0AVDD
+3.3VDDIO
2.5VDD
AGND
DGND
CLK
DATA CONT ADD
PORT A
CONTROL
OUTPUT
MUX
CIRCUITRY
CONTROL
PORT B
8-BIT DSP
LINK
OR
16-BIT
PARALLEL
OUTPUT
8-BIT DSP
LINK
OR
16-BIT
PARALLEL
OUTPUT
*DATA INTERLEAVING AND INTERPOLATING HB FILTER
RAM
COEF.
FILTER
RAM
COEF.
FILTER
RAM
COEF.
FILTER
RAM
COEF.
FILTER
NCO
NCO
NCO
NCO
RCIC2
RESAMPLER
CIC5
RCIC2
RESAMPLER
CIC5
RCIC2
RESAMPLER
CIC5
RCIC2
RESAMPLER
CIC5
VREF
ADC
CHANNEL
A
ADC
CHANNEL
B
SHA
SHA
MODE
SELECT
CLOCK
DUTY
CYCLE
STABILIZER
EXTERNAL
SYNC.
CIRCUIT
DDC
CLK
BUILT-IN
SELF-TEST
CIRCUITRY
PROGRAM
MICROPORT
83
3
AGC A*
AGC B*
Figure 1.


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