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AD6652BBC 数据表(PDF) 5 Page - Analog Devices

部件名 AD6652BBC
功能描述  12-Bit, 65 MSPS IF to Baseband Diversity Receiver
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6652BBC 数据表(HTML) 5 Page - Analog Devices

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AD6652
Rev. 0 | Page 5 of 76
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Table 1.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
AVDD
Full
IV
2.75
3.0
3.3
V
VDD
Full
IV
2.25
2.5
2.75
V
VDDIO
Full
IV
3.0
3.3
3.6
V
TAMBIENT
IV
−40
+25
+85
°C
ADC DC SPECIFICATIONS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 2.
Parameter (Conditions)
Temp
Test Level
Min
Typ
Max
Unit
RESOLUTION
Full
IV
12
Bits
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
IV
±5
±35
mV
Load Regulation @ 1.0 mA
Full
V
0.8
mV
Output Voltage Error (0.5 V Mode)
Full
V
±2.5
mV
Load Regulation @ 0.5 mA
Full
V
0.1
mV
INPUT REFERRED NOISE
Input Span = 1 V Internal
25°C
V
0.54
LSB rms
Input Span = 2 V Internal
25°C
V
0.27
LSB rms
ANALOG INPUT
Input Span = 1.0 V
Full
IV
1
V p-p
Input Span = 2.0 V
Full
IV
2
V p-p
Input Capacitance
Full
V
7
pF
REFERENCE INPUT RESISTANCE
Full
V
7
kΩ
MATCHING CHARACTERISTICS
Offset Error
Full
V
±0.1
% FSR
Gain Error
Full
V
±0.1
% FSR
ADC SWITCHING SPECIFICATIONS
AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 3.
Parameter (Conditions)
Temp
Test Level
Min
Typ
Max
Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
IV
65
MSPS
Minimum Conversion Rate
Full
V
1
MSPS
ACLK Period
Full
V
15.4
ns
ACLK Pulse Width High1
Full
V
6.2
ACLK/2
ns
ACLK Pulse Width Low1
Full
V
6.2
ACLK/2
ns
DATA OUTPUT PARAMETERS
Wake-Up Time2
Full
V
2.5
ms
OUT-OF-RANGE RECOVERY TIME
Full
V
2
Cycles
1 Duty cycle stabilizer enabled.
2 Wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.



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