AD6652BBC datasheet(31/76 Pages) AD

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AD6652

Rev. 0 | Page 31 of 76

MEMORY MAP ADDRE

ory

l register addresses that begin with 0x indicate that

that follows is in hexadecimal notation.

dress

modate register data that is 20 bits wide;

number(s), in decimal format, of the function that is being

described.

Eight, 3-bit external memory map addresses are shown in

decimal format in Table 22. Each of these addresses can

accommodate 8 bits of register data.

Decimal Addressing Example:

7:4 indicates that this is an

external memory address (no 0x prefix) and that the binary

address is 111, because only 3 external address bits are assigned.

Also, only Bit 4 of the 8-bit data field is described or referred to.

Hex Addressing Example:

0x0A:7–0 indicates that the binary

address is 00001010 and that Bits 7 through 0 are involved with

the function being described. Because this address begins with

0x, the user knows that it is not an external memory address,

and can be either an individual channel address register or an

output port control register, depending upon how it was routed

using the external memory address registers.

The largest 8-bit address that is used in the hexadecimal address

scheme is A9 or 169 decimal. This might not seem to be enough

memory addressing capacity, but, because addresses are re-used

with the external memory mapping scheme, there is no shortage

of address capability.

DDC INPUT MATRIX

The digital downconverter stages feature dual high speed

crossbar-switched input ports that allow the most flexibility in

routing the two ADC data streams to the four receive process-

ing channels. Crossbar switching means that any of the four

processing channels can receive data from either Port A or

Port B for a total of 16 possible combinations, as shown in

Table 12. Input port routing is selected in each NCO’s control

CONTROL REGISTER AND

SS NOTATIO

The following sections make frequent references to program-

mable registers and the memory mapping structure of the

AD6652. A good overview of the control registers and memory

mapping structure is found beginning in the External Mem

Map section. The following conventions are used in this

addressing scheme:

•

Contro

the address

•

cimal addresses are 8 bits wide, and each ad

All hexade

can accom

however, many of the available 20 bits per address are

unused.

•

A colon following an address indicates the specific bit

•

Table 12. Crossbar-Switched Routing of the Two 12-Bit ADC

Data Streams (A and B) Using the DDC Input Matrix

Channel 3

Channel 2

Channel 1

Channel 0

DDC DATA LATENCY

The overall signal path latency from DDC input to output can

be expressed in high speed clock cycles. Use the following

equation to calculate the latency:

Tlatency = MrCIC2 (MCICS + 7) + Ntaps + 26

where:

MrCIC2 and MCIC5 are decimation values for the rCIC2 and CIC5

filters, respectively.

Ntaps is the number RCF taps chosen.

GAIN SWITCHING

The AD6652 includes circuitry that is useful in applications in

which large dynamic range input signals exist. This circuitry

allows digital thresholds to be set such that an upper and a

lower threshold can be programmed.

One use of this circuitry is to detect when an ADC is about to

reach full scale with a particular input condition. The results

provide a flag can quickly insert an attenuator to prevent ADC

overdrive. If 18 dB (or any arbitrary value) of attenuation (or

gain) is switched in, then the signal dynamic range of the

system is increased by 18 dB. The process begins when the input

signal reaches the upper programmed threshold. In a typical

application, this might be set 1 dB (user definable) below full

scale. When this input condition is met, the appropriate LI (LIA,

LIA, LIB or LIB) signal associated with either the A or B input

port is made active. This can be used to switch the gain or

attenuation of the external circuit. The LI line stays active until

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