AD6652BBC datasheet(73/76 Pages) AD

73 / 76 page

AD6652

Rev. 0 | Page 73 of 76

AD6652 RECEIVER APPLICATIONS

One CDMA2000 IF Carrier with No External Analog

Filtering

Code Division Multiple Access depends upon a unique code

sequence that modulates the IF carrier along with the payload

data. This permits multiple signals to be transmitted on the

same carrier frequency and successfully separated at the

receiver. This technique spreads the spectrum of the initial

digital bit stream over a much wider bandwidth. The wideband

nature and stringent adjacent channel-filtering requirements of

CDMA2000 allow the AD6652 to process only one CDMA2000

channel. To do this requires the processing power of all four

channels operating at maximum speed.

Two CDMA2000 IF Carriers with External Analog Saw

Filtering

If two CDMA2000 carriers are to be processed by the AD6652,

prefiltering of the analog signal(s) going to the AD6652 is

required. Surface acoustic wave (SAW) filters are commonly

used to reduce the digital signal processing required of the

AD6652 filters. This combination permits adequate reduction

of the adjacent channel interference as specified for that

medium and permits two CDMA2000 carriers to be processed

using only two DDC channels per carrier.

Two UMTS or WCDMA IF Carriers with No External

Analog Saw Filtering

er requirements of wideband CDMA

TS, the AD665

MA carrier

sing p

nels for each carrie

f exte al analog filters.

aseband I and Q Processor

his application calls for baseband I and Q analog signals to be

outed individually to the two AD6652 ADC inputs. The 12-bit

DCs digitize the signals and send the data to all four receive

rocessing channels for decimation and filtering. Therefore,

ach channel is processing the same 12 bits of I data and 12 bits

f Q data simultaneously. The user can shut down unused

hannels as desired.

rocessing baseband I and Q data requires that each active

channel’s NCO and quadrature mixer be bypassed by program-

ming of the NCO control registers.

DESIGN GUIDELINES

When designing the AD6652 into a system, it is recommended

that, before starting design and layout, the designer become

familiar with these guidelines, which discuss the special circuit

connections and layout requirements required for certain pins.

The following power-up sequence is recommended for the

AD6652. First, ensure that RESET

APPLICATIONS

Due to less stringent filt

and UM

2 can receive two WCD

using the proces

ower of two chan

without the use o

is held logic low. Apply

AVDD (3.0 V) and VDD (2.5 V), allowing them both to

settle to nominal values before applying VDDIO (3.3 V).

Once VDDIO (3.3 V) has settled to nominal value, bring

RESET logic high. Last, apply a logic low RESET pulse for

30 ns to reset the AD6652 into a known state ready for

programming.

RESET pin: The RESET pin must be held logic low during

power-up sequencing to ensure that the internal logic starts

in a known state. Certain registers, noted in the datasheet,

are cleared after hardware reset. Failure to ensure hardware

reset during power-up might result in invalid output until a

valid reset is applied.

The number format used in this part is twos complement.

All input ports and output ports use twos complement data

format. The formats for individual internal registers are

given in the memory map description of these registers.

To enhance microport programming, the DTACK (RDY)

should be pulled high (to VDDIO)

ended val

ull-up

nd 5 kΩ.

externally using a

pull-up resister. The recomm

ue for the p

resistor is between 1 kΩ a

pin is used as chip select for programming with the

microport. It is recommended that the designer not tie this

pin low at all times. This pin should ideally be pulled high

using a pull-up resistor, and the user can pull it low

whenever microport control is required.

The output parallel port has one clock cycle overhead for

every output sample. So, if data from two AGCs with the

same data rate are output on one output port in 16-bit

interleaved I/Q mode along with the AGC word, then four

clock cycles are required for one sample from each

channel/AGC: one blank clock cycle, and one clock cycle

each for I data, Q data, and gain data.

AD6652BBC 数据表(PDF) 73 Page - Analog Devices

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