AD6652BBC datasheet(29/76 Pages) AD

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AD6652

Rev. 0 | Page 29 of 76

CTURE OVE

DATA INPUT MATRIX

into in-phase (I) and quadrature

(Q) components. This stage translates the input signal from a

digital intermediate frequency (IF) to digital baseband. Phase

and amplitude dither can be enabled on-chip to improve

spurious performance of the NCO. A phase-offset word is

available to create a known phase relationship between multiple

AD6652s or between channels.

SECOND-ORDER rCIC FILTER

Following frequency translation is a resampling, fixed

coefficient, high s

g cascade

integrator comb (rCIC2) filter, which reduces the sample rate

etween the master clock and the output data rate. This stage

can be bypassed by setting the decimation/interpolation ratio

to 1.

FIFTH-ORDER CIC FILTER

The next stage is a fifth-order cascaded integrator comb (CIC5)

filter, whose response is defined by the decimation rate. The

purpose of these filters is to reduce the data rate to the final

filter stage and to provide antialias filtering. The reduced data

rate allows the RAM coefficient filter (RCF) stage to calculate

more taps per output.

r beyond the 160 tap maximum.

s a

igerSHARC. A multiplexer for each port

Figure 45 illustrates the basic function of the AD6652, that is, to

select and filter a single carrier from a wide input spectrum and

to down-convert it to baseband data. Figure 46 shows examples

of the combined filter response of the rCIC2, CIC5, and RCF for

narrowband and wideband carriers.

DIGITAL DOWNCONVERTER ARCHITE

RVIEW

based on the ratio between the decimation and interpolation

registers. The resampler allows for noninteger relationships

RAM COEFFICIENT FILTER

The RAM coefficient filter (RCF) stage is a sum-of-products

FIR filter with programmable 20-bit coefficients, and decima-

tion rates programmable from 1 to 256 (1 to 32 in practice).

Each RAM coefficient FIR filter (RCF in Figure 1) can handle

maximum of 160 taps. Two or more RCF stages can be com-

bined using flexible channel configuration to increase the

processing powe

The digital downconverter (DDC) section features dual high

speed 12-bit input ports that are capable of crossbar multiplex-

ing of data to the four processing channels that follow the inpu

matrix. In addition, a third input option to the matrix is

available to facilitate BIST (built-in self-test). This option is a

pseudorandom noise (PN) sequence. The dual input ports

permit diversity reception of a carrier, or they can be treated as

unrelated and independent inputs. Either input port or the P

sequence can be routed to any or all four tuner channels. This

flexibility allows up to four signals to be processed simultane

ously. Refer to the DDC Input Matrix section for a

complete description.

NUMERICALLY CONTROLLED OSCILLATOR

Frequency translation is accomplished with a 32-bit complex

numerically controlled oscillator (NCO). Each of the four

processing channels contains a separate NCO. Real data

entering this stage is separated

peed, second-order, resamplin

The RCF outputs of each channel can be directly routed to one

or both output ports or to an AGC stage, where selected DDC

channels can be interleaved and interpolated in a half-band

filter, if desired.

INTERPOLATING HALF-BAND FILTERS AND AGC

Processed RCF data can also be routed to two half-band

interpolation stages, where up to four channels can be

combined (interleaved), interpolated by a factor of two, and

automatic gain control (AGC) applied. Each AGC stage ha

dynamic range of 96.3 dB. These stages can be bypassed

independently of each other. The outputs from the two AGC

stages are routed to both output port multiplexers. Each outpu

has a link port to permit seamless data interface with DSP

devices such as the T

selects one of the six data sources to appear at the device

parallel or link output pins.

The overall filter response for the AD6652 is the composite o

all decimating and interpolating stages. Each successive filter

stage is capable of narrower transition bandwidths, but requires

a greater number of CLK cycles to calculate the output. Mor

decimation in the first filter stage helps to minimize overal

power consumption.

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