DS31256 datasheet(119/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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read pointer, and sets the status bit for transmit DMA pending-queue read (TPQR) in the status register

for DMA (SDMA). See Section 5 for more details about status bits.

TDMAQ

Transmit DMA Queues Control

0880h

Bit #

Name

n/a

TDQF

TDQFE

TPQF

TPQFE

Default

Bit #

Name

n/a

TDQT2

TDQT1

TDQT0

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Transmit Pending-Queue FIFO Enable (TPQFE). This bit must be set to 1 to enable the DMA to burst

read descriptors from the pending queue. If this bit is set to 0, descriptors are read one at a time.

0 = pending-queue burst read disabled

1 = pending-queue burst read enabled

Bit 1/Transmit Pending-Queue FIFO Flush (TPQF). When this bit is set to 1, the internal pending-queue FIFO

is flushed (currently loaded pending-queue descriptors are lost). This bit must be set to 0 for proper operation.

0 = FIFO in normal operation

1 = FIFO is flushed

Bit 2/Transmit Done-Queue FIFO Enable (TDQFE). See Section 9.3.4 for details.

Bit 3/Transmit Done-Queue FIFO Flush (TDQF). See Section 9.3.4 for details.

Bits 8 to 10/Transmit Done-Queue Status Bit Threshold Setting (TDQT0 to TDQT2). See Section 9.3.4 for

more details.

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