DS31256 datasheet(118/183 Pages) MAXIM

118 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

118 of 183

Figure 9-18. Transmit Pending-Queue Structure

Once the transmit DMA is activated (by setting the TDE control bit in the master configuration register;

see Section 5), it can begin reading data out of the pending queue. It knows where to read the data by

reading the read pointer and adding it to the base address to obtain the actual 32-bit address. Once the

DMA has read the pending queue, it increments the read pointer by one dword. A check must be made to

ensure the incremented address does not exceed the transmit pending-queue end address. If the

incremented address does exceed this address, the incremented read pointer is set equal to 0000h.

Status/Interrupts

On each read of the pending queue by the DMA, the DMA sets the status bit for transmit DMA pending-

queue read (TPQR) in the status register for DMA (SDMA). The status bits can also (if enabled) cause

an hardware interrupt to occur. See Section 5 for more details.

Pending-Queue Burst Reading

The DMA can read the pending queue in bursts, which allows for a more efficient use of the PCI bus.

The DMA can grab descriptors from the pending queue in groups rather than one at a time, freeing up

the PCI bus for more time-critical functions.

An internal FIFO can store up to 16 pending-queue descriptors (16 dwords, since each descriptor

occupies one dword). The host must configure the pending-queue FIFO for proper operation through the

transmit DMA queues-control (TDMAQ) register (see the following).

When enabled through the transmit pending-queue FIFO-enable (TPQFE) bit, the pending-queue FIFO

does not read the pending queue until it is empty. When the pending queue is empty, it attempts to fill

the FIFO with additional descriptors by burst reading the pending queue. Before it reads the pending

queue, it checks (by examining the transmit pending-queue host write pointer) to ensure the pending

queue contains enough descriptors to fill the pending-queue FIFO. If the pending queue does not have

enough descriptors to fill the FIFO, it only reads enough to empty the pending queue. If the FIFO detects

that there are no pending-queue descriptors available for it to read, it waits and tries again later. If the

pending-queue FIFO can read descriptors from the pending queue, it burst reads them, increments the

Base + 00h

Base + 04h

Base + 08h

Base + 0Ch

Base + 10h

Base + 14h

Base + End Address

Pending-Queue Host Write Pointer

Pending-Queue DMA Read Pointer

Maximum of 65,536

Pending-Queue Descriptors

DMA Acquired

Pending-Queue Descriptor

Host Readied

Pending-Queue Descriptor

Host Readied

Pending-Queue Descriptor

Host Readied

Pending-Queue Descriptor

DMA Acquired

Pending-Queue Descriptor

DMA Acquired

Pending-Queue Descriptor

Host Readied

Pending-Queue Descriptor

DS31256 数据表(PDF) 118 Page - Maxim Integrated Products

DS31256 数据表(HTML) 118 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

DS31256 数据表(PDF) 118 Page - Maxim Integrated Products

DS31256 数据表(HTML) 118 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载