DS31256 datasheet(114/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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9.3.2 Packet Descriptors

A contiguous section of up to 65,536 quad dwords that make up the transmit packet descriptors resides in

main memory. The transmit packet descriptors are aligned on a quad-dword basis and can be placed

anywhere in the 32-bit address space through the transmit descriptor base address (Table 9-I). A data

buffer is associated with each descriptor. The data buffer can be up to 8188 Bytes long and must be a

contiguous section of main memory. The host informs the DMA of data buffers’ actual sizes through the

byte count field that resides in the packet descriptor.

If an outgoing packet requires more space than the data buffer allows, then packet descriptors are link-

listed together by the host to provide a chain of data buffers. Figure 9-15 shows an example of how three

descriptors were linked together for an incoming packet on HDLC channel 7. Channel 3 only required a

single data buffer and thus only one packet descriptor was used. Figure 9-10 shows a similar example for

channels 5 and 1.

Packet descriptors can be either pending (i.e., queued up by the host and ready for transmission by the

DMA) or completed (i.e., have been transmitted by the DMA and are available for processing by the

host). Pending-packet descriptors are pointed to by the pending-queue descriptors and completed packet

descriptors are pointed to by the done-queue descriptors.

Table 9-I. Transmit Descriptor Address Storage

NAME

ADDRESS

Transmit Descriptor Base Address 0 (lower word)

TDBA0

0850h

Transmit Descriptor Base Address 1 (upper word)

TDBA1

0854h

Figure 9-15. Transmit Descriptor Example

CH 5 Single Sent Buffer Descriptor

Base + 00h

CH 7 1st Queued Buffer Descriptor

Base + 10h

Base + 20h

CH 7 Sent 1st Buffer Descriptor

Base + 30h

Free Descriptor

Base + 40h

Base + 50h

Free Descriptor

Base + 60h

Base + 70h

CH 7 Last Sent Buffer Descriptor

Base + 80h

Free Descriptor

Base + FFFD0h

Free Descriptor

Base + FFFF0h

CH 3 Single Queued Buffer Desc.

CH 7 2nd Queued Buffer Descriptor

CH 7 Last Queued Buffer Descriptor

Pending-Queue Descriptor Address

Done-Queue Descriptor Pointer

Maximum of 65,536 Descriptors

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