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DS31256 数据表(PDF) 175 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 175 Page - Maxim Integrated Products |
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175 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 175 of 183 AC CHARACTERISTICS: JTAG TEST PORT INTERFACE (VDD = 3.0V to 3.6V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JTCLK Clock Period t1 1000 ns JTCLK Clock Low Time t2 400 ns JTCLK Clock High Time t3 400 ns JTMS/JTDI Setup Time to the Rising Edge of JTCLK t4 50 ns JTMS/JTDI Hold Time from the Rising Edge of JTCLK t5 50 ns Delay Time from the Falling Edge of JTCLK to Data Valid on JTDO t6 2 50 ns Figure 13-6. JTAG Test Port Interface AC Timing Diagram JTCLK JTMS/JTDI JTDO t4 t5 t6 t1 t2 t3 |
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