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AR8327-AL1A-R 数据表(PDF) 102 Page - List of Unclassifed Manufacturers |
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AR8327-AL1A-R 数据表(HTML) 102 Page - List of Unclassifed Manufacturers |
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102 / 394 page ![]() 102 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 102 • June 2011 COMPANY CONFIDENTIAL Table 3-67. Window Rule Control Register 1 3.4.8 WIN_RULE_CTRL2 Address 0x0220 SFT&HW RST Table 3-68 summarizes the WIN_RULE_CTRL2 Register 2 Table 3-68. Window Rule Control Register 2 Bit R/W Inital Value Mnemonic Description 31:28 R/O 0 RESERVED 27:24 R/W 0 L4_LENGTH_1 These bit indicate that window rule in port0 to select length of L4, from L4_OFFSET_1. 23:20 R/W 0 L3_LENGTH_1 These bit indicate that window rule in port0 to select length of L3, from L3_OFFSET_1. 19:16 R/W 0 L2_LENGTH_1 These bit indicate that window rule in port0 to select length of L2, from L2_OFFSET_1. 15 R/W 0 RESERVED 14:10 R/W 0 L4_OFFSET_1 These bit indicate that window rule in port0 to select offset of L3, from TCP/UDP header. 9:5 R/W 0 L3_OFFSET_1 These bit indicate that window rule in port0 to select offset of L3, from IP header. 4:0 R/W 0 L2_OFFSET_1 These bit indicate that window rule in port0 to select offset of L2, from MAC DA. Bit R/W Inital Value Mnemonic Description 31:28 R/O 0 RESERVED 27:24 R/W 0 L4_LENGTH_2 These bit indicate that window rule in port0 to select length of L4, from L4_OFFSET_2. 23:20 R/W 0 L3_LENGTH_2 These bit indicate that window rule in port0 to select length of L3, from L3_OFFSET_2. 19:16 R/W 0 L2_LENGTH_2 These bit indicate that window rule in port0 to select length of L2, from L2_OFFSET_2. 15 R/W 0 RESERVED 14:10 R/W 0 L4_OFFSET_2 These bit indicate that window rule in port0 to select offset of L3, from TCP/UDP header. 9:5 R/W 0 L3_OFFSET_2 These bit indicate that window rule in port0 to select offset of L3, from IP header. 4:0 R/W 0 L2_OFFSET_2 These bit indicate that window rule in port0 to select offset of L2, from MAC DA. |
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