AR8327-AL1A-R datasheet(104/394 Pages) ETC2

104 / 394 page

104 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

104 • June 2011

COMPANY CONFIDENTIAL

3.4.11

WIN_RULE_CTRL5

Address 0x022C

SFT&HW RST

Table 3-71 summarizes the WIN_RULE_CTRL5 Register 5

Table 3-71.

Window Rule Control Register 5

3.4.12

WIN_RULE_CTRL6

Address 0x0230

SFT&HW RST

Table 3-72 summarizes the WIN_RULE_CTRL6 Register 6

9:5

R/W

L3_OFFSET_4

These bit indicate that window rule in port0 to

select offset of L3, from IP header.

4:0

R/W

L2_OFFSET_4

These bit indicate that window rule in port0 to

select offset of L2, from MAC DA.

Bit

R/W

Inital

Value

Mnemonic

Description

Bit

R/W

Inital

Value

Mnemonic

Description

31:28

R/O

RESERVED

27:24

R/W

L4_LENGTH_5

These bit indicate that window rule in

port0 to select length of L4, from

L4_OFFSET_5.

23:20

R/W

L3_LENGTH_5

These bit indicate that window rule in

port0 to select length of L3, from

L3_OFFSET_5.

19:16

R/W

L2_LENGTH_5

These bit indicate that window rule in

port0 to select length of L2, from

L2_OFFSET_5.

R/W

RESERVED

14:10

R/W

L4_OFFSET_5

These bit indicate that window rule in

port0 to select offset of L3, from TCP/

UDP header.

9:5

R/W

L3_OFFSET_5

These bit indicate that window rule in

port0 to select offset of L3, from IP

header.

4:0

R/W

L2_OFFSET_5

These bit indicate that window rule in

port0 to select offset of L2, from MAC

DA.

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