AR8327-AL1A-R datasheet(296/394 Pages) ETC2

296 / 394 page

296 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

296 • June 2011

COMPANY CONFIDENTIAL

Table 3-291, “ACL_28 Rate Limit Control Register 0,” on page 296 summerizes the

ACL_RATE_CTRL0_28 Register 0

Table 3-291.

ACL_28 Rate Limit Control Register 0

3.7.141 ACL_RATE_CTRL1_28

Address 0x0AE4

SFT&HW RST

Table 3-292, “ACL_28 Rate Limit Control Register 1,” on page 296 summerizes the

ACL_RATE_CTRL1_28 Register 1

Table 3-292.

ACL_28 Rate Limit Control Register 1

Bit

R/W

Inital

Value

Mnemonic

Description

31:18

R/O

RESERVED

17:15

R/W

ACL_CBS_28

Commited burst size for ingress rate

limit

14:0

R/W

0x7FFF

ACL_CIR_28

Ingress Rate Limit for all priority.

Rate is limited to times of 32kbps.

Default 15'h7FFF is for disable rate

limit for ingress. if these bits are set to

15'h0, no frame should be received in

from this port.

Bit

R/W

Inital

Value

Mnemonic

Description

31:24

R/O

RESERVED

R/W

ACL_BORROW_EN_28

Borrow enable

R/W

ACL_RATE_UNIT_28

1: Packets/ 0: bytes

R/W

ACL_CF_28

Coupling flag for ingress rate limit

R/W

ACL_CM_28

Color mode for ingress rate limit

19:18

R/W

2'b01

ACL_RATE_TIME_SLOT_28

ACL Ingress rate limit control timer

slot.

2'b00: 100us;

2'b01: 1ms

2'b10: 10ms

2'b11: 100ms

Notes: if port rate limit set to less than

96kbps, don't select 100us as time slot

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