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AR8327-AL1A-R 数据表(PDF) 355 Page - List of Unclassifed Manufacturers

部件名 AR8327-AL1A-R
功能描述  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

AR8327-AL1A-R 数据表(HTML) 355 Page - List of Unclassifed Manufacturers

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Atheros Communications, Inc.
AR8327/AR8327N Seven-port Gigabit Ethernet
Switch
•
355
3.10.11 1000Base-T Status Register
Address Offset: 0x0A, or 0d10
11
Master/Slave
Configuratio
n
Mode
R/W
The value of this bit will be updated immediately after
writing this register. But the value written to this bit does
not takes effect until any one of the following occurs:
o Software reset is asserted (register 0.15)
o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down
to normal operation
o Link goes down
Register 9.11 is ignored if register 9.12 is equal to 0.
1 = Manual configure as MASTER
0 = Manual configure as SLAVE
HW Rst
0
SW Rst
Update
10
Port Type
Mode
R/W
The value of this bit will be updated immediately after
writing this register. But the value written to this bit does
not takes effect until any one of the following occurs:
o Software reset is asserted (register 0.15)
o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down
to normal operation
o Link goes down
Register 9.10 is ignored if register 9.12 is equal to 1.
1 = Prefer multi-port device (MASTER)
0 = Prefer single port device (SLAVE)
HW Rst
0
SW Rst
Update
9
1000Base-T
Full Duplex
Mode
R/W
The value of this bit will be updated immediately after
writing this register. But the value written to this bit does
not takes effect until any one of the following occurs:
o Software reset is asserted (register 0.15)
o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down
to normal operation
o Link goes down
1 = Advertise
0 = Not advertised
HW Rst
1
SW Rst
Update
8
1000Base-T
Half-Duplex
Mode
R/W
The value of this bit will be updated immediately after
writing this register. But the value written to this bit does
not takes effect until any one of the following occurs:
o Software reset is asserted (register 0.15)
o Restart Auto-Negotiation is asserted (register 0.9)
o Power down (register 0.11) transitions from power down
to normal operation
o Link goes down
1 = Advertise
0 = Not advertised
Note: the default setting is no 1000 baset/half duplex
advertised
HW Rst
0
SW Rst
Update
7:0
Reserved
Mode
R/W
HW Rst
0
SW Rst
0
Bit
Symbol
Type
Description



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