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DS31256 数据表(PDF) 122 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 122 Page - Maxim Integrated Products |
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122 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 122 of 183 Figure 9-20. Transmit Done-Queue Structure Once the transmit DMA is activated (through the TDE control bit in the master configuration register; see Section 5 for more details), it can begin writing data to the done queue. It knows where to write data into the done queue by reading the write pointer and adding it to the base address to obtain the actual 32- bit address. Once the DMA writes to the done queue, it increments the write pointer by one dword. A check must be made to ensure the incremented address does not exceed the transmit done-queue end address. If the incremented address does exceed this address, the incremented write pointer is set equal to 0000h (i.e., the base address). Status Bits/Interrupts On writes to the done queue by the DMA, the DMA sets the status bit for the transmit DMA done-queue write (TDQW) in the status register for DMA (SDMA). The host can configure the DMA to either set this status bit on each write to the done queue or only after multiple (from 2 to 128) writes. The host controls this by setting the TDQT0 to TDQT2 bits in the transmit DMA queues-control (TDMAQ) register. See the description of the TDMAQ register at the end of this section for more details. The DMA also checks the transmit done-queue host read pointer to ensure that an overflow does not occur. If this does occur, the DMA sets the status bit for transmit DMA done-queue write error (TDQWE) in the status register for DMA (SDMA), and it does not write to the done queue nor does it increment the write pointer. In such a scenario, information on transmitted packets is lost and unrecoverable. Each of the status bits can also (if enabled) cause a hardware interrupt to occur. See Section 5 for more details. Done-Queue Burst Writing The DMA can write to the done queue in bursts. This allows for a more efficient use of the PCI bus. The DMA can hand off descriptors to the done queue in groups rather than one at a time, freeing up the PCI bus for more time-critical functions. An internal FIFO can store up to eight done-queue descriptors (8 dwords, since each descriptor occupies one dword). The host must configure the FIFO for proper operation through the transmit DMA queues control (TDMAQ) register (see the following). dmatdq Base + 00h Base + 04h Base + 08h Base + 0Ch Base + 10h Base + 14h Base + End Address Done Queue DMA Write Pointer Done Queue Host Read Pointer Maximum of 65536 Done Queue Descriptors DMA Readied Done Queue Descriptor DMA Readied Done Queue Descriptor DMA Readied Done Queue Descriptor DMA Readied Done Queue Descriptor Host Processed Done Queue Descriptor Host Processed Done Queue Descriptor Host Processed Done Queue Descriptor |
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