DS31256 datasheet(120/183 Pages) MAXIM

120 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

120 of 183

9.3.4 Done Queue

The DMA writes to the transmit done queue when it has finished either transmitting a complete packet

chain or a complete data buffer. This option is selected by the host when it configures the DQS field in

the transmit DMA configuration RAM (Section 9.3.5). The descriptor location is indicated in the done

queue through a 16-bit pointer that the host uses along with the transmit descriptor base address to find

the exact 32-bit address of the associated transmit descriptor.

Figure 9-19. Transmit Done-Queue Descriptor

dword 0

unused

Status (3)

CHRST

PRI

HDLC Channel (8)

Descriptor Pointer (16)

Note: The organization of the done queue is not affected by the enabling of Big Endian.

dword 0; Bits 0 to 15/Descriptor Pointer. This 16-bit value is the offset from the transmit descriptor base

address to either the first descriptor in a HDLC packet (can be a single descriptor) that has been transmitted

(DQS = 0) or the descriptor that corresponds to a single data buffer that has been transmitted (DQS = 1).

dword 0; Bits 16 to 23/HDLC Channel Number. HDLC channel number, which can be from 1 to 256.

00000000 (00h) = HDLC channel number 1

11111111 (FFh) = HDLC channel number 256

dword 0; Bit 24/Priority Packet (PRI). This field is meaningless in the done queue and could be set to any value.

See Section 9.3.3 for details.

dword 0; Bit 25/Channel Reset (CHRST). This field is meaningless in the done queue and could be set to any

value. See Section 9.3.3 for details.

dword 0; Bits 26 to 28/Packet Status. These three bits report the final status of an outgoing packet. All the error

states cause a HDLC abort sequence (eight 1s in a row, followed by continuous interfill bytes of either FFh or

7Eh) to be sent, and the channel is placed out of service by the transmit DMA, setting the channel enable (CHEN)

bit in the transmit DMA configuration RAM to 0. The status state of 000 is only used when the channel has been

configured by the host to write to the done queue only after a complete HDLC packet (can be a single data buffer)

has been transmitted (i.e., DQS = 0). The status states of 001, 010, and 011 are only used when the channel has

been configured by the host to write to the done queue after each data buffer has been transmitted (i.e., DQS = 1).

000 = packet transmission complete and the descriptor pointer field corresponds to the first

descriptor in a HDLC packet (can be a single descriptor) that has been transmitted (DQS = 0)

001 = first buffer transmission complete of a multi (or single) buffer packet (DQS = 1)

010 = middle buffer transmission complete of a multibuffer packet (DQS = 1)

011 = last buffer transmission complete of a multibuffer packet (DQS = 1)

100 = software provisioning error; this channel was not enabled

101 = descriptor error; either byte count = 0 or channel code inconsistent with pending queue

110 = PCI error

111 = transmit FIFO error; it has underflowed

dword 0; Bits 29 to 31/Unused. Not used by the DMA. Could be any value when read.

DS31256 数据表(PDF) 120 Page - Maxim Integrated Products

DS31256 数据表(HTML) 120 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载