DS31256 datasheet(150/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

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Table 11-B. Local Bus 8-Bit Width Address,

LBHE Setting

PCBE [3:0]

LBHE

1110

1101

1011

0111

Note 1: All other possible states for

PCBE cause the device to return a target abort to the host.

Note 2: The 8-bit data picked from the PCI bus is routed/sampled to/from the LD[7:0] signal lines.

Note 3: If no

PCBE signals are asserted during an access, a target abort is not returned and no transaction occurs on the local bus.

If the local bus is used as 16-bit bus, the LBW control bit must be set to 0. In 16-bit accesses, the host

can either perform 16-bit access or an 8-bit access by asserting the appropriate

PCBE signals (Table

11-C). For 16-bit access, the host enables the combination of either

PCBE0/PCBE1 or PCBE2/PCBE3

and the local bus block maps the word from/to the PCI bus to/from the LD[15:0] signals. For 8-bit access

in the 16-bit bus mode, the host must assert just one of the

PCBE0 to PCBE3 signals. If the host asserts a

combination of

PCBE signals not supported by the local bus, the local bus rejects the access and the PCI

block returns a target abort to the host. See Section 10 for details on a target abort. Section 11.3 contains

a number of timing examples for the local bus.

Table 11-C. Local Bus 16-Bit Width Address, LD,

LBHE Setting

PCBE [3:0]

8/16

LD[15:8]

LD[7:0]

LBHE

1110

Active

1101

Active

1100

Active

1011

Active

0111

Active

0011

Active

Note 1: All other possible states for

PCBE cause the device to return a target abort to the host.

Note 2: The 16-bit data picked from the PCI bus is routed/sampled to/from the LD[7:0] and LD[15:8] signal lines as shown.

Note 3: If no

PCBE signals are asserted during an access, a target abort is not returned and no transaction occurs on the local bus.

Bridge Mode Bus Arbitration

In bridge mode, the local bus can arbitrate for bus access. In order for this feature to operate, the host

must access the PCI bridge mode control register (LBBMC) and enable it through the LARBE control bit

(the default is bus arbitration disabled). If bus arbitration is enabled, then, before a bus transaction can

occur, the local bus first requests bus access by asserting the LHOLD

(LBR) signal and then waits for the

bus to be granted from the local bus arbiter by sensing that the LHLDA (

LBG) has been asserted. If the

host on the PCI bus attempts a local bus access when the local bus is not granted by the local bus master

(

LBGACK is deasserted), the local bus block immediately informs the host by issuing a PCI target retry

that the local bus is busy and cannot be accessed at that time (in other words, come back later). See

Section 10 for details about the PCI target retry. When this happens, the local bus block does not attempt

the bus access and keeps the LA, LD,

LBHE, LWR (LR/W), and LRD (LDS) signals tri-stated.

If the host attempts a local bus access when the bus is busy, the local bus block requests bus access, and,

after it has been granted, it seizes the bus for the time programmed into the local bus arbitration timer

(LAT0 to LAT3 in the LBBMC register), which can be from 32 to 1,048,576 clocks. As long as the local

bus has been granted and the arbitration timer has at least 16 clocks left, the host is allowed to access the

local bus. See Figure 11-4 and the timing examples in Section 11.3 for more details.

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