EDB8164B4PR-1DITF-R datasheet(45/152 Pages) MICRON

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Figure 16: tFAW Timing (8-Bank Devices)

CK_c

CK_t

CA[9:0]

Tn+

Tm+

Tx+

Ty + 1

Ty + 2

Tz + 1

Tz + 2

Bank

ACTIVATE

NOP

CMD

Bank

ACTIVATE

NOP

Bank

ACTIVATE

NOP

Bank

ACTIVATE

NOP

Bank

NOP

Bank

ACTIVATE

NOP

Bank

tRRD

tFAW

tRRD

Note:

1. Exclusively for 8-bank devices.

Read and Write Access Modes

After a bank is activated, a READ or WRITE command can be issued with CS_n LOW,

CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at

this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a

WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst

READ or burst WRITE operation on successive clock cycles.

A new burst access must not interrupt the previous 4-bit burst operation when BL = 4.

When BL = 8 or BL = 16, a READ can be interrupted by a READ and a WRITE can be

interrupted by a WRITE, provided that the interrupt occurs on a 4-bit boundary and

that tCCD is met.

Burst READ Command

The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2

HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and

CA1f–CA9f, determine the starting column address for the burst. The read latency (RL)

is defined from the rising edge of the clock on which the READ command is issued to

the rising edge of the clock from which the tDQSCK delay is measured. The first valid

data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock when the

READ command is issued. The data strobe output is driven LOW tRPRE before the first

valid rising strobe edge. The first bit of the burst is synchronized with the first rising

edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-

aligned with the data strobe. The RL is programmed in the mode registers.

Pin input timings for the data strobe are measured relative to the crosspoint of DQS and

its complement, DQS#.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Read and Write Access Modes

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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