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EDB8164B4PR-1DITF-R 数据表(PDF) 73 Page - Micron Technology |
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EDB8164B4PR-1DITF-R 数据表(HTML) 73 Page - Micron Technology |
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73 / 152 page ![]() Figure 46: All-Bank REFRESH Operation AB PRECHARGE NOP T0 T1 T2 T3 T4 Tx Tx + 1 Ty Ty + 1 CK_c CK_t CA[9:0] CMD NOP REFab NOP REFab ≥tRPab ≥tRFCab ≥tRFCab NOP Valid NOP Figure 47: Per-Bank REFRESH Operation AB PRECHARGE REFRESH to bank 0 NOP T0 T1 Tx Tx + 1 Tx + 2 Ty Ty + 1 Tz Tz + 1 CK_c CK_t CA[9:0] CMD NOP REFpb NOP REFpb ≥tRPab ≥tRFCpb ≥tRFCpb NOP ACTIVATE NOP Bank 1 Row A Row A REFRESH to bank 1 ACTIVATE command to bank 1 Notes: 1. Prior to T0, the REFpb bank counter points to bank 0. 2. Operations to banks other than the bank being refreshed are supported during the tRFCpb period. SELF REFRESH Operation The SELF REFRESH command can be used to retain data in the array, even if the rest of the system is powered down. When in the self refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate the SELF REFRESH operation. The SELF REFRESH command is executed by taking CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the clock cycle following the POWER-DOWN command. Once the command is registered, CKE must be held LOW to keep the device in self-refresh mode. The mobile LPDDR2 device can operate in self refresh mode in both the standard and extended temperature ranges. The device also manages self refresh power consumption when the operating temperature changes, resulting in the lowest possible power con- sumption across the operating temperature range (See IDD Specifications for details). After the device has entered self refresh mode, all external signals other than CKE are “Don’t Care.” For proper self refresh operation, power supply pins (VDD1, VDD2, and VDDQ) must be at valid levels. VDDQ can be turned off during self refresh. If VDDQ is turned off, VREFDQ must also be turned off. Prior to exiting self refresh, both VDDQ and 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM SELF REFRESH Operation 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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