EDB8164B4PR-1DITF-R datasheet(29/152 Pages) MICRON

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3. RESET Command

After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional

PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at

least tINIT4 while keeping CKE asserted and issuing NOP commands.

4. MRRs and Device Auto Initialization (DAI) Polling

After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit com-

mands are supported. After Te, CKE can go LOW in alignment with power-down entry

and exit specifications (see Power-Down).

The MRR command can be used to poll the DAI bit, which indicates when device auto

initialization is complete; otherwise, the controller must wait a minimum of tINIT5 or

until the DAI bit is set before proceeding.

Because the memory output buffers are not properly configured by Te, some AC param-

eters must use relaxed timing specifications before the system is appropriately config-

ured.

After the memory device sets the DAI bit (MR0, DAI) to zero, indicating DAI complete,

the device is in the idle state (Tf ). DAI status can be determined by issuing the MRR

command to MR0.

The device sets the DAI bit no later than tINIT5 after the RESET command. The control-

ler must wait at least tINIT5 or until the DAI bit is set before proceeding.

5. ZQ Calibration

After tINIT5 (Tf ), the MRW initialization calibration (ZQ calibration) command can be

issued to the memory (MR10).

This command is used to calibrate output impedance over process, voltage, and tem-

perature. In systems where more than one Mobile LPDDR2 device exists on the same

bus, the controller must not overlap MRW ZQ calibration commands. The device is

ready for normal operation after tZQINIT.

6. Normal Operation

After (Tg), the MRW command must be used to properly configure the memory, includ-

ing, for example, output buffer drive strength, latencies,and so on. Specifically, MR1,

MR2, and MR3 must be set to configure the memory for the target frequency and mem-

ory configuration.

After the initialization sequence is complete, the device is ready for any valid command.

After Tg, the clock frequency can be changed using the procedure described in Input

Clock Frequency Changes and Stop Events.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Power-Up and Initialization

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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