EDB8164B4PR-1DITF-R datasheet(6/152 Pages) MICRON

6 / 152 page

Figure 51: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 78

Figure 52: Temperature Sensor Timing ........................................................................................................... 80

Figure 53: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2 ............................................................. 81

Figure 54: MODE REGISTER WRITE Timing – RL = 3, tMRW = 5 ....................................................................... 82

Figure 55: ZQ Timings ................................................................................................................................... 84

Figure 56: Power-Down Entry and Exit Timing ................................................................................................ 86

Figure 57: CKE Intensive Environment ........................................................................................................... 86

Figure 58: REFRESH-to-REFRESH Timing in CKE Intensive Environments ...................................................... 86

Figure 59: READ to Power-Down Entry ........................................................................................................... 87

Figure 60: READ with Auto Precharge to Power-Down Entry ............................................................................ 88

Figure 61: WRITE to Power-Down Entry ......................................................................................................... 89

Figure 62: WRITE with Auto Precharge to Power-Down Entry .......................................................................... 90

Figure 63: REFRESH Command to Power-Down Entry .................................................................................... 91

Figure 64: ACTIVATE Command to Power-Down Entry ................................................................................... 91

Figure 65: PRECHARGE Command to Power-Down Entry ............................................................................... 91

Figure 66: MRR Command to Power-Down Entry ........................................................................................... 92

Figure 67: MRW Command to Power-Down Entry .......................................................................................... 92

Figure 68: Deep Power-Down Entry and Exit Timing ....................................................................................... 93

Figure 69: VREF DC Tolerance and VREF AC Noise Limits ................................................................................. 108

Figure 70: LPDDR2-466 to LPDDR2-1066 Input Signal ................................................................................... 110

Figure 71: LPDDR2-200 to LPDDR2-400 Input Signal ..................................................................................... 111

Figure 72: Differential AC Swing Time and tDVAC .......................................................................................... 112

Figure 73: Single-Ended Requirements for Differential Signals ....................................................................... 114

Figure 74: VIX Definition ............................................................................................................................... 115

Figure 75: Differential Input Slew Rate Definition for CK_t, CK_c, DQS_t, and DQS_c ...................................... 116

Figure 76: Single-Ended Output Slew Rate Definition ..................................................................................... 118

Figure 77: Differential Output Slew Rate Definition ........................................................................................ 119

Figure 78: Overshoot and Undershoot Definition ........................................................................................... 120

Figure 79: HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 121

Figure 80: Output Driver ............................................................................................................................... 122

Figure 81: Output Impedance = 240 Ohms, I-V Curves After ZQRESET ............................................................ 125

Figure 82: Output Impedance = 240 Ohms, I-V Curves After Calibration ......................................................... 126

Figure 83: Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock ................................................. 141

Figure 84: Typical Slew Rate – tIH for CA and CS_n Relative to Clock ............................................................... 142

Figure 85: Tangent Line – tIS for CA and CS_n Relative to Clock ...................................................................... 143

Figure 86: Tangent Line – tIH for CA and CS_n Relative to Clock ..................................................................... 144

Figure 87: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe ............................................................. 148

Figure 88: Typical Slew Rate – tDH for DQ Relative to Strobe ........................................................................... 149

Figure 89: Tangent Line – tDS for DQ with Respect to Strobe .......................................................................... 150

Figure 90: Tangent Line – tDH for DQ with Respect to Strobe .......................................................................... 151

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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