EDB8164B4PR-1DITF-R datasheet(27/152 Pages) MICRON

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Figure 11: Simplified State Diagram

Power

applied

Resetting

Self

refreshing

Refreshing

Power-on

Resetting

MR reading

Idle

MR reading

Active

MR reading

Active

power-down

Idle

power-down

Deep

power-down

Idle1

Active

BST

PR,PRA

Precharging

MR writing

Writing

Reading

with

auto precharge

Writing

with

auto precharge

Resetting

power-down

RESET

MRR

PDX

DPDX

DPD

REF

WRA

RDA

Automatic sequence

Command sequence

PR = PRECHARGE

PRA = PRECHARGE ALL

ACT = ACTIVATE

WR(A) = WRITE (with auto precharge)

RD(A) = READ (with auto precharge)

BST = BURST TERMINATE

RESET = RESET is achieved through

MRW command

MRW = MODE REGISTER WRITE

MRR = MODE REGISTER READ

PD = enter power-down

PDX = exit power-down

SREF = enter self refresh

SREFX = exit self refresh

DPD = enter deep power-down

DPDX = exit deep power-down

REF = REFRESH

PR, PRA

ACT

Note:

1. All banks are precharged in the idle state.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Simplified State Diagram

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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