EDB8164B4PR-1DITF-R datasheet(74/152 Pages) MICRON

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VREFDQ must be within their respective minimum/maximum operating ranges (see the

Single-Ended AC and DC Input Levels for DQ and DM table). VREFDQ can be at any level

between 0 and VDDQ; VREFCA can be at any level between 0 and VDD2 during self refresh.

Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (See AC

and DC Logic Input Measurement Levels for Single-Ended Signals for details). After en-

tering self refresh mode, the device initiates at least one all-bank REFRESH command

internally during tCKESR. The clock is internally disabled during SELF REFRESH opera-

tion to save power. The device must remain in self refresh mode for at least tCKESR. The

user can change the external clock frequency or halt the external clock one clock after

self refresh entry is registered; however, the clock must be restarted and stable before

the device can exit SELF REFRESH operation.

Exiting self refresh requires a series of commands. First, the clock must be stable prior

to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least

equal to the self refresh exit interval (tXSR), must be satisfied before a valid command

can be issued to the device. This provides completion time for any internal refresh in

progress. For proper operation, CKE must remain HIGH throughout tXSR. NOP com-

mands must be registered on each rising clock edge during tXSR.

Using self refresh mode introduces the possibility that an internally timed refresh event

could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting

self refresh, at least one REFRESH command (one all-bank command or eight per-bank

commands) must be issued before issuing a subsequent SELF REFRESH command.

Figure 48: SELF REFRESH Operation

Exit

Valid

NOP

Enter

NOP

Enter self refresh mode

Input clock frequency can be changed

or clock can be stopped during self refresh.

Valid

tCKESR (MIN)

tXSR (MIN)

tIHCKE

tISCKE

Exit self refresh mode

Don’t Care

2 t

(MIN)

CK_t

CS_n

CK_c

CMD

CKE

Notes:

1. Input clock frequency can be changed or stopped during self refresh, provided that

upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the

clock frequency is between the minimum and maximum frequencies for the particular

speed grade.

2. The device must be in the all banks idle state prior to entering self refresh mode.

3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.

4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during

tXSR.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

SELF REFRESH Operation

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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