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EDB8164B4PR-1DITF-R 数据表(PDF) 69 Page - Micron Technology |
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EDB8164B4PR-1DITF-R 数据表(HTML) 69 Page - Micron Technology |
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69 / 152 page ![]() Figure 42: Regular Distributed Refresh Pattern 0ms 32ms 64ms 96ms tREFBW tREFBW tREFI tREFI Notes: 1. Compared to repetitive burst REFRESH with subsequent REFRESH pause. 2. As an example, in a 1Gb LPDDR2 device at TC ≤ 85˚C, the distributed refresh pattern has one REFRESH command per 7.8 μs; the burst refresh pattern has one REFRESH command per 0.52 μs, followed by ≈ 30ms without any REFRESH command. 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM REFRESH Command 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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