EDB8164B4PR-1DITF-R datasheet(7/152 Pages) MICRON

7 / 152 page

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 1

Table 2: S4 Configuration Addressing ............................................................................................................... 1

Table 3: Package Codes and Descriptions ......................................................................................................... 2

Table 4: IDD Specifications – Dual Die, Dual Channel ...................................................................................... 10

Table 5: IDD6 Full-Array Self Refresh Current at 45°C for Dual die product ........................................................ 12

Table 6: IDD6 Partial-Array Self Refresh Current at 85°C for Dual die product .................................................... 12

Table 7: IDD Specifications – Dual Die, Dual Channel ...................................................................................... 13

Table 8: IDD6 Partial-Array Self Refresh Current at 105°C Dual die for Dual die prodct ....................................... 15

Table 9: Ball/Pad Descriptions ....................................................................................................................... 24

Table 10: Initialization Timing Parameters ...................................................................................................... 30

Table 11: Power-Off Timing ............................................................................................................................ 31

Table 12: Mode Register Assignments ............................................................................................................. 32

Table 13: MR0 Device Information (MA[7:0] = 00h) ......................................................................................... 33

Table 14: MR0 Op-Code Bit Definitions .......................................................................................................... 33

Table 15: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 33

Table 16: MR1 Op-Code Bit Definitions .......................................................................................................... 33

Table 17: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) ................................. 34

Table 18: No-Wrap Restrictions ...................................................................................................................... 35

Table 19: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 35

Table 20: MR2 Op-Code Bit Definitions .......................................................................................................... 36

Table 21: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 36

Table 22: MR3 Op-Code Bit Definitions .......................................................................................................... 36

Table 23: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 36

Table 24: MR4 Op-Code Bit Definitions .......................................................................................................... 37

Table 25: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 37

Table 26: MR5 Op-Code Bit Definitions .......................................................................................................... 37

Table 27: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 38

Table 28: MR6 Op-Code Bit Definitions .......................................................................................................... 38

Table 29: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 38

Table 30: MR7 Op-Code Bit Definitions .......................................................................................................... 38

Table 31: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 38

Table 32: MR8 Op-Code Bit Definitions .......................................................................................................... 38

Table 33: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 39

Table 34: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 39

Table 35: MR10 Op-Code Bit Definitions ........................................................................................................ 39

Table 36: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh) ......................................................................................... 40

Table 37: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 40

Table 38: MR16 Op-Code Bit Definitions ........................................................................................................ 40

Table 39: MR16 Bank and OP corresponding table .......................................................................................... 40

Table 40: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 41

Table 41: MR17 PASR Segment Mask Definitions (1Gb - 8Gb only) ................................................................... 41

Table 42: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 41

Table 43: Reserved Mode Registers ................................................................................................................. 42

Table 44: MR32 DQ Calibration Pattern A (MA[7:0] = 20H) ............................................................................... 42

Table 45: MR40 DQ Calibration Pattern B (MA[7:0] = 28H) ............................................................................... 42

Table 46: MR63 RESET (MA[7:0] = 3Fh) – MRW Only ....................................................................................... 42

Table 47: Bank Selection for PRECHARGE by Address Bits ............................................................................... 59

Table 48: PRECHARGE and Auto Precharge Clarification ................................................................................. 63

Table 49: REFRESH Command Scheduling Separation Requirements .............................................................. 65

Table 50: Bank and Segment Masking Example ............................................................................................... 75

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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