EDB8164B4PR-1DITF-R datasheet(8/152 Pages) MICRON

8 / 152 page

Table 51: Temperature Sensor Definitions and Operating Conditions .............................................................. 79

Table 52: Data Calibration Pattern Description ............................................................................................... 82

Table 53: Truth Table for MRR and MRW ........................................................................................................ 82

Table 54: Command Truth Table .................................................................................................................... 94

Table 55: CKE Truth Table .............................................................................................................................. 96

Table 56: Current State Bank n to Command to Bank n Truth Table ................................................................. 97

Table 57: Current State Bank n to Command to Bank m Truth Table ................................................................ 99

Table 58: DM Truth Table .............................................................................................................................. 101

Table 59: Absolute Maximum DC Ratings ...................................................................................................... 102

Table 60: Input/Output Capacitance ............................................................................................................. 102

Table 61: Switching for CA Input Signals ........................................................................................................ 103

Table 62: Switching for IDD4R ......................................................................................................................... 103

Table 63: Switching for IDD4W ........................................................................................................................ 104

Table 64: IDD Specification Parameters and Operating Conditions .................................................................. 104

Table 65: Recommended DC Operating Conditions ....................................................................................... 106

Table 66: Input Leakage Current ................................................................................................................... 106

Table 67: Operating Temperature Range ........................................................................................................ 107

Table 68: Single-Ended AC and DC Input Levels for CA and CS_n Inputs ......................................................... 107

Table 69: Single-Ended AC and DC Input Levels for CKE ................................................................................ 107

Table 70: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 108

Table 71: Differential AC and DC Input Levels ................................................................................................ 112

Table 72: CK_t/CK_c and DQS_t/DQS_c Time Requirements Before Ringback (tDVAC) ................................... 113

Table 73: Single-Ended Levels for CK_t, CK_c, DQS_t, DQS_c ......................................................................... 114

Table 74: Crosspoint Voltage for Differential Input Signals (CK_t, CK_c, DQS_t, DQS_c) .................................. 115

Table 75: Differential Input Slew Rate Definition ............................................................................................ 116

Table 76: Single-Ended AC and DC Output Levels .......................................................................................... 116

Table 77: Differential AC and DC Output Levels ............................................................................................. 117

Table 78: Single-Ended Output Slew Rate Definition ...................................................................................... 117

Table 79: Single-Ended Output Slew Rate ...................................................................................................... 118

Table 80: Differential Output Slew Rate Definition ......................................................................................... 119

Table 81: Differential Output Slew Rate ......................................................................................................... 119

Table 82: AC Overshoot/Undershoot Specification ......................................................................................... 120

Table 83: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 122

Table 84: Output Driver Sensitivity Definition ................................................................................................ 123

Table 85: Output Driver Temperature and Voltage Sensitivity ......................................................................... 123

Table 86: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 123

Table 87: I-V Curves ..................................................................................................................................... 124

Table 88: Definitions and Calculations .......................................................................................................... 127

Table 89: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................... 128

Table 90: Refresh Requirement Parameters (Per Density) ............................................................................... 131

Table 91: AC Timing ..................................................................................................................................... 131

Table 92: CA and CS_n Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) .......................................... 138

Table 93: CA and CS_n Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) .......................................... 138

Table 94: Derating Values for AC/DC-Based tIS/tIH (AC220) ........................................................................... 139

Table 95: Derating Values for AC/DC-Based tIS/tIH (AC300) ........................................................................... 139

Table 96: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC) ....................................................... 139

Table 97: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ....................................................... 145

Table 98: Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) ....................................................... 146

Table 99: Derating Values for AC/DC-Based tDS/tDH (AC220) ........................................................................ 146

Table 100: Derating Values for AC/DC-Based tDS/tDH (AC300) ....................................................................... 147

Table 101: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC) ....................................................... 147

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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