EDB8164B4PR-1DITF-R datasheet(81/152 Pages) MICRON

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Figure 53: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2

MRR

NOP1

NOP

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

DQ0

DQ[7:1]

DQ8

DQ[15:9]

DQ16

DQ[23:17]

DQ24

DQ[31:25]

RL = 3

Transitioning data

Optionally driven the same as DQ0 or 0b

tMRR = 2

0011

Reg 40

Reg 32

MRR

0011

Pattern A

Pattern B

x32

x16

Notes:

1. The MRR command has a burst length of four.

2. The MRR operation must not be interrupted.

3. A MRR to MR32 and MR40 drives valid data on DQ[0] during the entire burst. For a x16

device, DQ[8] drives the same information as DQ[0] during the burst. For a x32 device,

DQ[8], DQ[16], and DQ[24] drive the same information as DQ[0] during the burst.

4. For a x16 device, DQ[7:1] and DQ[15:9] may optionally drive the same information as

DQ[0], or they may drive 0b during the burst. For a x32 device, DQ[7:1], DQ[15:9],

DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0], or they

may drive 0b during the burst.

5. The MODE REGISTER command period is tMRR. No command (other than NOP) is al-

lowed during this period.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

MODE REGISTER READ

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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