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EDB8164B4PR-1DITF-R 数据表(PDF) 51 Page - Micron Technology |
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EDB8164B4PR-1DITF-R 数据表(HTML) 51 Page - Micron Technology |
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51 / 152 page  Figure 24: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 Bank n col addr Col addr READ NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK# CK CA[9:0] CMD DQS# DQS DQ RL = 3 WL = 1 BL/2 Transitioning data NOP NOP NOP NOP tDQSCK tDQSSmin WRITE D IN A0 D IN A1 D D OUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP Bank n col addr Col addr The minimum time from the burst READ command to the burst WRITE command is defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles. Note that if a READ burst is truncated with a burst TERMINATE (BST) command, the effective burst length of the truncated READ burst should be used for BL when calculating the minimum READ-to-WRITE delay. Figure 25: Seamless Burst READ – RL = 3, BL = 4, tCCD = 2 Bankn col addr a Col addr a READ NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK# CK CA[9:0] CMD DQS# DQS DQ RL = 3 Transitioning data READ NOP NOP NOP tCCD = 2 NOP D OUT B0 D OUT B1 D OUT B2 D OUT B3 D OUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP Bankn col addr b Col addr b A seamless burst READ operation is supported by enabling a READ command at every other clock cycle for BL = 4 operation, every fourth clock cycle for BL = 8 operation, and every eighth clock cycle for BL = 16 operation. This operation is supported as long as the banks are activated, whether the accesses read the same or different banks. 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Burst READ Command 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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