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EDB8164B4PR-1DITF-R 数据表(PDF) 97 Page - Micron Technology |
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EDB8164B4PR-1DITF-R 数据表(HTML) 97 Page - Micron Technology |
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97 / 152 page  Table 55: CKE Truth Table (Continued) Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care” Current State CKEn-1 CKEn CS_n Command n Operation n Next State Notes All banks idle H L H NOP Enter idle power-down Idle power-down H L L Enter self re- fresh Enter self refresh Self refresh H L L DPD Enter deep power-down Deep power-down Resetting H L H NOP Enter resetting power-down Resetting power-down Other states H H Refer to the command truth table Notes: 1. Current state = the state of the device immediately prior to the clock rising edge n. 2. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 3. CKEn = the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the previous clock edge. 4. CS_n= the logic state of CS_n at the clock rising edge n. 5. Command n = the command registered at clock edge n, and operation n is a result of command n. 6. Power-down exit time (tXP) must elapse before any command other than NOP is issued. 7. The clock must toggle at least twice prior to the tXP period. 8. Upon exiting the resetting power-down state, the device will return to the idle state if tINIT5 has expired. 9. The DPD exit procedure must be followed as described in Deep Power Down. 10. Self refresh exit time (tXSR) must elapse before any command other than NOP is issued. 11. The clock must toggle at least twice prior to the tXSR time. Table 56: Current State Bank n to Command to Bank n Truth Table Notes 1–5 apply to all parameters and conditions Current State Command Operation Next State Notes Any NOP Continue previous operation Current state Idle ACTIVATE Select and activate row Active Refresh (per bank) Begin to refresh Refreshing (per bank) 6 Refresh (all banks) Begin to refresh Refreshing (all banks) 7 MRW Load value to mode register MR writing 7 MRR Read value from mode register Idle, MR reading RESET Begin device auto initialization Resetting 7, 8 PRECHARGE Deactivate row(s) in bank or banks Precharging 9, 10 Row active READ Select column and start read burst Reading WRITE Select column and start write burst Writing MRR Read value from mode register Active MR reading PRECHARGE Deactivate row(s) in bank or banks Precharging 9 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Truth Tables 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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