EDB8164B4PR-1DITF-R datasheet(101/152 Pages) MICRON

101 / 152 page

5. A BST command cannot be issued to another bank; it applies only to the bank represen-

ted by the current state.

6. These states must not be interrupted by any executable command. NOP commands must

be applied during each clock cycle while in these states:

Idle MRR: Starts with registration of the MRR command and ends when tMRR has been

met. After tMRR is met, the device is in the all banks idle state.

Reset MRR: Starts with registration of the MRR command and ends when tMRR has been

met. After tMRR is met, the device is in the all banks idle state.

Active MRR: Starts with registration of the MRR command and ends when tMRR has

been met. After tMRR is met, the bank is in the active state.

MRW: Starts with registration of the MRW command and ends when tMRW has been

met. After tMRW is met, the device is in the all banks idle state.

7. BST is supported only if a READ or WRITE burst is ongoing.

8. tRRD must be met between the ACTIVATE command to bank n and any subsequent

ACTIVATE command to bank m.

9. READs or WRITEs listed in the command column include READs and WRITEs with or

without auto precharge enabled.

10. This command may or may not be bank-specific. If all banks are being precharged, they

must be in a valid state for precharging.

11. MRR is supported in the row-activating state.

12. MRR is supported in the precharging state.

13. The next state for bank m depends on the current state of bank m (idle, row-activating,

precharging, or active).

14. A WRITE command can be issued after the completion of the READ burst; otherwise a

BST must be issued to end the READ prior to asserting a WRITE command.

15. A READ command can be issued after the completion of the WRITE burst; otherwise, a

BST must be issued to end the WRITE prior to asserting another READ command.

16. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be

followed by any valid command to other banks provided that the timing restrictions in

the PRECHARGE and Auto Precharge Clarification table are met.

17. Not bank-specific; requires that all banks are idle and no bursts are in progress.

18. RESET command is achieved through MODE REGISTER WRITE command.

Table 58: DM Truth Table

Functional Name

Notes

Write enable

Valid

Write inhibit

Note:

1. Used to mask write data, and is provided simultaneously with the corresponding input

data.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Truth Tables

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

101

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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