EDB8164B4PR-1DITF-R datasheet(25/152 Pages) MICRON

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Functional Description

Mobile LPDDR2 is a high-speed SDRAM internally configured as a 4- or 8-bank memory

device. The device uses a double data rate architecture on the command/address (CA)

bus to reduce the number of input pins in the system. The 10-bit CA bus is used to

transmit command, address, and bank information. Each command uses one clock cy-

cle, during which command information is transferred on both the rising and falling

edges of the clock.

The LPDDR2-S4 device uses a double data rate architecture on the DQ pins to achieve

high- speed operation. The double data rate architecture is essentially a 4n prefetch ar-

chitecture with an interface designed to transfer two data bits per DQ every clock cycle

at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a

single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four

corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write access is burst oriented; access starts at a selected location and contin-

ues for a programmed number of locations in a programmed sequence.

Access begins with the registration of an ACTIVATE command followed by a READ or

WRITE command. Registered address and BA bits that coincide with the ACTIVATE

command are used to select the row and bank to be accessed. Registered address bits

that coincide with the READ or WRITE command are used to select the bank and the

starting column location for the burst access.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Functional Description

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB8164B4PR-1DITF-R 数据表(PDF) 25 Page - Micron Technology