EDB8164B4PR-1DITF-R datasheet(127/152 Pages) MICRON

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Table 88: Definitions and Calculations

Symbol

Description

Calculation

Notes

tCK(avg) and

nCK

The average clock period across any consecutive

200-cycle window. Each clock period is calculated

from rising clock edge to rising clock edge.

Unit tCK(avg) represents the actual clock average

tCK(avg)of the input clock under operation. Unit

nCK represents one clock cycle of the input clock,

counting from actual clock edge to actual clock

edge.

tCK(avg)can change no more than ±1% within a

100-clock-cycle window, provided that all jitter

and timing specifications are met.

tCK(avg) =

Σ tCK

j /N

Where N = 200

j = 1

tCK(abs)

The absolute clock period, as measured from one

rising clock edge to the next consecutive rising

clock edge.

tCH(avg)

The average HIGH pulse width, as calculated

across any 200 consecutive HIGH pulses.

tCH(avg) =

Σ tCH

(N × tCK(avg))

Where N = 200

j = 1

tCL(avg)

The average LOW pulse width, as calculated

across any 200 consecutive LOW pulses.

tCL(avg) =

Σ tCL

/(N × tCK(avg))

Where N = 200

j = 1

tJIT(per)

The single-period jitter defined as the largest de-

viation of any signal tCK from tCK(avg).

tJIT(per) = min/max of tCK

i –

tCK(avg)

Where i = 1 to 200

tJIT(per),act

The actual clock jitter for a given system.

tJIT(per),

allowed

The specified clock period jitter allowance.

tJIT(cc)

The absolute difference in clock periods between

two consecutive clock cycles. tJIT(cc) defines the

cycle-to-cycle jitter.

tJIT(cc) = max of tCK

i + 1 –

tCK

tERR(nper)

The cumulative error across n multiple consecu-

tive cycles from tCK(avg).

tERR(nper) =

Σ tCK

– (n × tCK(avg))

i + n – 1

j = i

tERR(nper),act

The actual cumulative error over n cycles for a

given system.

tERR(nper),

allowed

The specified cumulative error allowance over n

cycles.

tERR(nper),min The minimum tERR(nper).

tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min

tERR(nper),max The maximum tERR(nper).

tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Clock Specification

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

127

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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