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26HS01GTAM03 数据表(PDF) 28 Page - Infineon Technologies AG |
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26HS01GTAM03 数据表(HTML) 28 Page - Infineon Technologies AG |
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28 / 166 page ![]() Datasheet 28 of 166 002-12337 Rev. *Y 2022-01-18 256Mb/512Mb/1Gb SEMPER™ Flash HYPERBUS™ interface, 1.8V/3.0V Features 4.1.1.2 ECC error address trap (EATV) • A 32-bit register is provided to capture the ECC data unit address where an ECC error is first encountered during a read of the flash array. Only the address of the first enabled error type (“2-bit only” or “1-bit or 2-bit” as selected in CFR2x[6]) encountered after POR, hardware reset, or the ECC Clear transaction is captured. The EATV Register is only updated during Read transactions. The EATV Register contains the address that was accessed when the error was detected. The failing bits may not be located at the exact address indicated in the register, but will be located within the aligned 16-byte ECC data unit where the error was detected. If errors are found in multiple ECC data units during a single read operation, only the address of the first failing ECC unit address is captured in the EATV Register. When 2-bit error detection is not enabled and the same ECC unit is programmed more than once, ECC error detection for that ECC unit is disabled, therefore no error is recognized to trap the address. • The Address Trap Register can be read using HYPERBUS™ or Legacy (x1) SPI Address Trap Register read trans- action. • Clear ECC Status Register transaction, POR, or CS# Signaling/Hardware/Software reset clears the Address Trap Register. Table 11 Error upper / lower address trap register bit assignments Density Error lower address register Error upper address register All 256Mb 512Mb 1Gb EATV[15] A15 0 0 0 EATV[14] A14 0 0 0 EATV[13] A13 0 0 0 EATV[12] A12 0 0 0 EATV[11] A11 0 0 0 EATV[10] A10 0 0 0 EATV[9] A9 0 0 A25 EATV[8] A8 0 A24 A24 EATV[7] A7 A23 A23 A23 EATV[6] A6 A22 A22 A22 EATV[5] A5 A21 A21 A21 EATV[4] A4 A20 A20 A20 EATV[3] A3 A19 A19 A19 EATV[2] A2 A18 A18 A18 EATV[1] A1 A17 A17 A17 EATV[0] A0 A16 A16 A16 |
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