26HS01GTAM03 datasheet(90/166 Pages) INFINEON

90 / 166 page

Datasheet

90 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.1

5.2

HYPERBUS™ registers

5.2.1

Configuration register 1 (CFR1x) (x8)

Configuration Register 1 controls device functionality.

Table 66

Bit number

Name

Function

Read/write

Factory

default

(binary)

Description

REGNAME#T[x]

T = N, V, O

Descending Order

––

Possible Options:

N/A - Not Applicable

R - Readable Only

R/W - Readable and Writable

R/1 - Readable and One Time Program-

mable

Possible

Options:

Format:

Description of the Configuration bit

0 = Option ‘0’ selection of the Bit

1 = Option '1' selection of the Bit

Dependency: Is this Bit part of a function which

requires multiple bits for implementation?

Table 67

Configuration register 1 (x8)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

CFR1N[15]

CFR1V[15]

DPDPOR

Deep Power Down

power saving mode

entry selection upon

Power-On-Reset

N => R/W

V => R/W

Description:

The DPDPOR bit selects if the device will be in either the Deep

Power Down (DPD) mode or the Standby mode after the

completion of Power-On-Reset (POR). If enabled, DPDPOR

configures the device to start in DPD mode to reduce current

consumption until the device is needed. If the device is in DPD,

a pulse on CS# or a Hardware reset will return the device to

Standby mode.

Selection Options:

0 = Power Down Power mode is entered upon the completion

of Power-On-Reset

1 = Standby mode is entered upon the completion of

Power-On-Reset Deep

Dependency: N/A

CFR1N[14:12]

CFR1V[14:12]

IOIMPD[2:0] I/O Driver Output

Impedance Selection

N => R/W

V => R/W

101

Description:

The IOIMPD[2:0] bits select the IO driver output impedance

(drive strength). The output impedance configuration bits

adjust the drive strength during normal device operation to

meet system signal integrity requirements.

Selection Options:

000 = 45Ω

001 = 120Ω

010 = 90Ω

011 = 60Ω

100 = 45Ω

101 = 30Ω (Factory Default)

110 = 20Ω

111 = 15Ω

Dependency: N/A

CFR1N[11]

CFR1V[11]

TLCFRP

Temporary Locking

selection of Configu-

ration Registers

N => R/W

V => R/W

Description:

The TLCFRP bit temporarily protects the Configuration

Registers. Upon power-up or a hardware reset, TLCFRP is set

to its default state. When selected, it protects the Configu-

ration registers from programming.

Note It is recommended to program and verify other Config-

uration Register bits before setting up TLCFRP = 0.

Selection Options:

0 = Configuration Registers are protected

1 = Configuration Registers are not protected

Dependency: N/A

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