26HS01GTAM03 datasheet(71/166 Pages) INFINEON

71 / 166 page

Datasheet

71 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.10.2.4

Program SSR transaction

The Program Secure Silicon transaction (PRSSR_4_1) programs data in the SSR, which is in a different address

space from the main array data and is OTP. The SSR is 1024 bytes, so the address bits from A31 to A10 must be

zero for this transaction.

The PRGERR bit in STR1V[6] may be checked to determine if any error occurred during the operation.

To program the OTP array in bit granularity, the rest of the bits within a data byte can be set to 1.

Each SSR memory space can be programmed one or more times, provided that the region is not locked.

Attempting to program zeros in a region that is locked will fail with the PRGERR bit in STR1V[6] set to 1.

Programming once, even in a protected area does not cause an error and does not set PRGERR bit. Subsequent

programming can be performed only on the unprogrammed bits (that is, 1 data). Programming more than once

within an ECC unit will disable ECC on that data unit.

4.10.2.5

Program persistent protection bit (PPB)

The Program Persistent Protect Bit (PRPPB_4_0) transaction programs a bit in the PPB Register to protect the

sector of the provided address from being programed or erased.

The PRGERR bit in STR1V[6] may be checked to determine if any error occurred during the operation. Program

PPB bit transaction will abort when trying to program the PPB bits protected by ASPPPB (ASPO[3]), ASPPRM

(ASPO[0]) and PPBLCK (PPLV[0]) bit.

4.10.3

HYPERBUS™ program related registers and transactions

4.10.4

Legacy (x1) SPI program related registers and transactions

Table 52

HYPERBUS™ program related registers and transactions

Related registers

(see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions

(see Table 120 on page 124)

HYPERBUS™ Status Register (STR1V)

Program Word (PGWORD_4_0)

HYPERBUS™ Configuration Register 1 (CFR1N, CRF1V)

Program POR Time Register (PRNPOR_4_0)

Program Volatile Interrupt Configuration Register (PGVINC_4_0)

Program Volatile Interrupt Status Register (PGVINS_4_0)

Program Volatile Configuration Register 1 (PGVCR1_4_0)

Program Volatile Configuration Register 2 (PGVCR2_4_0)

Program Nonvolatile Configuration Register 1 (PGNCR1_4_0)

Program Nonvolatile Configuration Register 2 (PGNCR2_4_0)

Program One-Time-Programmable Advanced Sector Protection Register

(PGOASP_2_1)

Program Nonvolatile Password (PGNPWD_2_1)

Program Nonvolatile AutoBoot Register (RDATBN_1_0)

Program One-Time-Programmable EnduraFlex Registers [4:0]

(PGOENX_2_1)

HYPERBUS™ Advance Sector Protect Register (ASPO)

Program Secure Silicon Region Word (PG_SSR_4_1)

HYPERBUS™ ASP PPB Lock (PPLV)

Program Nonvolatile Persistent Protection Bits (PGNPPB_2_1)

Set Volatile Dynamic Protection Bits (STVDYB_2_1)

Clear ECC Error Status Failure Flags (CLRECC_1_1)

Clear Status Register Failure Flags (CLVSTR_1_0)

Table 53

Legacy (x1) SPI program related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

SPI Status Register 1 (STR1N, STR1V)

Write Enable (WRENB_0_0)

SPI Advance Sector Protect Register (ASPO)

Program Secure Silicon (PRSSR_4_1)

SPI ASP PPB Lock (PPLV)

Program Persistent Protection Bit (PRPPB_4_0)

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