26HS01GTAM03 datasheet(74/166 Pages) INFINEON

74 / 166 page

Datasheet

74 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.11.3

Erase status and count

4.11.3.1

Evaluate erase status transaction

The Evaluate Erase Status (EVERST_1_0) transaction verifies that the last erase operation on the addressed

sector was completed successfully. If the selected sector was successfully erased, then the erase status bit

(SESTAT - STRV[0]) is set to 1. If the selected sector was not completely erased STRV[0] is 0.

The Evaluate Erase Status transaction can be used to detect when erase operations that have failed due to loss

of power, reset, or failure during the erase operation. The transaction requires tEES to complete and update the

erase status in STRV. The RDYBSY bit (STRV[7]) can be read to determine when the Evaluate Erase Status trans-

action is completed. If a sector is found not erased with STRV[0] = 0, the sector must be erased again to ensure

reliable storage of data in the sector.

4.11.3.2

Read sector erase count register transaction

The Read Sector Erase Count (RDSECV_1_0) transaction outputs the number of erase cycles for the addressed

sector. The erase cycle count is stored in the Sector Erase Count (SECV[22:0]) Register. Load Sector Address

(LDSRAD_2_1) initiates loading the Sector Erase Count Register.

The transaction requires tSEC to complete and update the SECV[22:0] Register. The RDYBSY bit may be read to

determine when the Sector Erase Count Transaction finished. The SECV[23] bit is used to determine if the

reported sector erase count is corrupted and was reset.

4.11.3.3

Blank check transaction

The Blank Check (BLKCHK_1_0) transaction will confirm if the selected Flash Memory Array sector is fully erased.

The Blank Check command does not allow for reads to the array during the Blank Check. Reads to the array while

this command is executing will return unknown data.

The Blank Check command may not be written while the device is actively programming or erasing or suspended.

Use the Status Register read to confirm if the device is still busy and when complete if the sector is blank or not.

Bit 7 of the Status Register will show if the device is performing a Blank Check (similar to an erase operation). Bit

5 of the Status Register will be cleared to 0 if the sector is erased and set to 1 if not erased.

As soon as any bit is found to not be erased, the device will halt the operation and report the results.

Once the Blank Check is completed, the EAC will return to the Standby state.

4.11.4

Legacy (x1) SPI

Before any erase transaction can be accepted by the device, a Write Enable (WRENB_0_0) transaction must be

issued and decoded by the device. Erase transactions can only be executed by the device if the Write/Program

Enable bit (WRPGEN) in the Status Register is set to ‘1’ to enable erase operations. When an erase transaction is

completed, the WRPGEN bit is reset to a ‘0’.

While the erase transaction is in progress, the Status Register 1 may be read to check the value of the Device

Ready/Busy (RDYBSY) bit. The RDYBSY bit is a ‘1’ during the self-timed erase transaction, and is a ‘0’ when it is

completed.

The ERSERR bit in STR1V[5] can be checked to determine if any error occurred during the erase transaction.

An erase transaction applied to a sector that has been Write Protected through the Block Protection bits or ASP,

will not be executed and will set the ERSERR status fail bit.

Erase transactions will be initiated when CS# is driven into the logic High state.

4.11.5

Erase 4KB sector transaction

The Erase 4KB Sector (ER004_4_0) transaction sets all the bits of a 4KB sector to 1 (all bytes are FFh).

This transaction is ignored when the device is configured for uniform sectors only (CFR3V[3] = 1). If the Erase 4KB

sector transaction is issued to a non-4KB sector address, the device will abort the operation and will not set the

ERSERR status fail bit.

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