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26HS01GTAM03 数据表(PDF) 34 Page - Infineon Technologies AG

部件名 26HS01GTAM03
功能描述  256Mb/512Mb/1Gb SEMPER??Flash HYPERBUS??interface, 1.8V/3.0V
PDF  166 Pages
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制造商  INFINEON [Infineon Technologies AG]
网页  http://www.infineon.com
标志 INFINEON - Infineon Technologies AG

26HS01GTAM03 数据表(HTML) 34 Page - Infineon Technologies AG

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002-12337 Rev. *Y
2022-01-18
256Mb/512Mb/1Gb SEMPER™ Flash
HYPERBUS™ interface, 1.8V/3.0V
Features
4.3
Interface CRC
Interface CRC performs a hardware accelerated CRC calculation on the communication between a host and the
device, ensuring the integrity of information transferred. A CRC is an error-detecting code commonly used in
devices to detect accidental changes to raw data.
The Interface CRC method in HL-T/HS-T family devices relies entirely on the host to verify the CRC check-value
and take appropriate actions. The device calculates the CRC check-value which the host reads using the Read
Interface CRC transaction (RDCRC_4_0, RICRC_1_1). The check-value calculated includes all transaction contents
while CS# is LOW, namely command, address and data. This CRC checksum can be generated across either a
single transaction or a set of transactions. The only limitation is that the data size over which the slave is calcu-
lating the CRC checksum must be less than 232 bits.
The host must also calculate the CRC check-value over the same transaction sequence. When ready, the host can
read the device’s calculated CRC check-value and compare it with its own. If there is a mismatch, the host can
choose to repeat the complete transaction sequence.
Figure 22
CRC calculation overview
Note At the end of the CRC read transaction, the device resets the CRC check-value and reinitializes the CRC
polynomial.
CRC32 Polynomial: X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 + X9 + X8 + X6 + 1
Notes
• The CRC polynomial between the host and the device must be identical.
• The Interface CRC check-value will reset to 0xFFFFFFFFh under the following conditions:
-POR
-Hardware Reset
-Software Reset
- CS# Signaling Reset
- A read of the Interface CRC check-value
- Exit from Deep Power Down
• If a transaction is aborted before the command is legally received, i.e. the transfer length is cut short by CS#
deasserting early - the transferred data will still be clocked into the CRC check-value, but it is no longer
guaranteed. When using Interface CRC, only valid, non-aborted transactions must be used.
• It is required to read Interface CRC value before any Volatile Status Register read and Clear Interface CRC value
after any volatile Status Register read(s).
• When Interface CRC is disabled, the interface CRC Register value becomes indeterminate. It is recommended
to read the interface CRC Register before disabling the interface CRC feature, and again after enabling the
interface CRC feature to re-initialize the CRC calculation.
CK
CS#
Command
(16 Bits)
Address
(32 Bits)
Read Data
(n Bits)
Command
(16 Bits)
Address
(32 Bits)
Write Data
(n Bits)
DQ[7:0]
Read Transaction
Program Transaction
CRC32 - Equation
CRC Read
Every 32-bits of data is shifted into
CRC32 and the Checksum is updated



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