26HS01GTAM03 datasheet(45/166 Pages) INFINEON

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Datasheet

45 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.5.2

Secure silicon region (SSR)

Each device has a 1024B OTP SSR address space that is separate from the Flash Memory Array. The SSR area is

divided into 32, individually lockable, 32-Byte aligned and length regions.

In the 32-Byte region starting at address zero:

• The 16 lowest address bytes are programmed by CYPRESS™ with a 128-bit random number. Only CYPRESS™ is

able to program these bytes. Attempting to program 0s into these locations will fail and generate a Program

Status Error.

• The next four higher address bytes (SSR Lock bytes) are used to provide one bit per SSR region to permanently

protect each region from programming. The bytes are erased when shipped from CYPRESS™. After an SSR region

is programmed, it can be locked to prevent further programming, by programming the related protection bit

in the SSR Lock bytes.

• The next higher 12B of the lowest address region are Reserved for Future Use (RFU). The bits in these RFU bytes

may be programmed by the host system but it must be understood that a future device may use those bits for

protection of a larger SSR space. The bytes are erased when shipped from CYPRESS™.

The remaining regions are erased when shipped from CYPRESS™, and are available for programming of

additional permanent data.

See Figure 31 for a pictorial representation of the SSR memory space.

The SSR memory space is intended for increased system security. SSR values, such as the random number

programmed by CYPRESS™, can be used to ‘mate’ a flash component with the system CPU / ASIC to prevent

device substitution.

In HYPERBUS™, the Configuration Register Temporary Locking selection of SSR (CFR1x[10]) bit protects the entire

SSR memory space from programming when cleared. This allows trusted boot code to control programming of

SSR regions then set the Locking bit to prevent further SSR memory space programming during the remainder

of normal power-on system operation.

Figure 31

OTP protection (Nonvolatile)

4.5.2.1

Reading the SSR memory space

In HYPERBUS™ interface, reading the SSR Region is performed once the SSR ASO is entered using the SSR entry

sequence. The SSR is mapped to a specific sector identified during the SSR Entry command sequence. SSR Read

operations within the sector identified during the SSR Entry command sequence but outside the valid 1KB SSR

address range will yield indeterminate data. Reads to sectors not overlaid by the SSR ASO will retrieve array data.

A SSR Exit sequence will return the device to the array read ASO.

In Legacy (x1) SPI interface, reading the SSR Region is performed using Read SSR transaction (RDSSR_4_0).

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