26HS01GTAM03 datasheet(9/166 Pages) INFINEON

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Datasheet

9 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Interface overview

Figure 2

Logic block diagram

The SEMPER™ Flash family consists of multiple densities with, 1.8V and 3.0V core and I/O voltage options.

The device control logic is subdivided into two parallel operating sections: the Host Interface Controller (HIC) and

the embedded algorithm controller (EAC). The HIC monitors signal levels on the device inputs and drives outputs

as needed to complete read, program and write data transfers with the host system. The HIC delivers data from

the currently entered address map on read transfers; places write transfer address and data information into the

EAC command memory, and notifies the EAC of power transition, and write transfers. The EAC interrogates the

command memory, after a program or write transfer, for legal command sequences and performs the related

embedded algorithms (EA).

Changing the nonvolatile data in the memory array requires a sequence of operations that are part of EA. The

algorithms are managed entirely by the internal EAC. The main algorithms perform programming and erase of

the main flash array data. The host system writes command codes to the flash device. The EAC receives the

command, performs all the necessary steps to complete the transaction, and provides status information during

the progress of an EA.

In addition to the mandatory signals CS#, CK, SI/DQ0, SO/DQ1, DQ [7:2] and DS, the SEMPER™ Flash devices also

include optional signals CK#, RESET#, INT# and RSTO#. When RESET# transitions from LOW to HIGH the device

returns to the default state that occurs after an internal POR. The DS is synchronized with the output data during

read transactions enabling host system to capture data at high clock frequency operation. The INT# is an

open-drain output can provide an interrupt to the HYPERFLASH™ master to indicate when the HYPERFLASH™

transitions from busy to ready at the end of a program or erase operation or to indicate the detection of an ECC

error during read. The RSTO# is an open-drain output used to indicate when a POR is occurring within the device

and can be used as a system level reset signal. Upon completion of the internal POR the RSTO# signal will

transition from LOW to HIGH impedance after a user defined timeout period has expired. Upon transition to the

HIGH impedance state, the external pull-up resistance will pull RSTO# HIGH and the device immediately is placed

into the Standby state.

Infineon Endurance Flex architecture provides system designers the ability to customize SEMPER™ Flash’s

endurance and retention for their specific application. The host defines partitions for high endurance or long

retention, providing up to 1+ million cycles or 25 years of data retention.

SEMPER™ Flash devices support error detection and correction by generating an embedded hamming ECC during

memory array programming. This ECC code is then used for single-bit and double-bit error detection and

single-bit correction during read.

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