26HS01GTAM03 datasheet(53/166 Pages) INFINEON

53 / 166 page

Datasheet

53 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.8

Read transactions

HL-T/HS-T supports different read transactions, namely: Read Memory array, Read Device Identification, Read

use any of following two interfaces/protocols:

• Legacy (x1) SPI interface with SDR

• HYPERBUS™ interface with DDR

These read transactions use the following features:

• The read transactions require latency cycles following the command/address bytes to allow time to access the

memory array (except RDAY1_4_0 and RDAY1_C_0 of Legacy (x1) SPI protocol).

• Data Strobe (DS), available only in HYPERBUS™, is an output clock which is edge aligned with read data enabling

the memory controller to capture data (see Data strobe (DS) - HYPERBUS™ on page 57).

• The read transaction has the option of wrapped, hybrid, or linear bursts.

4.8.1

Read identification transactions

There are three unique identification transactions, each supporting the two protocols (Legacy (x1) SPI) and

(HYPERBUS™).

4.8.1.1

Read device identification transaction

The Read Device Identification (RDIDN_0_0, RDIDSF_1_1) transaction provides read access to manufacturer

identification and device identification. The Legacy (x1) SPI mode has no address cycles. In SPI mode, the trans-

action uses latency cycles set by (CFR3V[7:6]) to enable maximum clock frequency of 166MHz under. Similarly in

HYPERBUS™ mode, latency cycles set by (CFR1V[7:4]) to enable maximum clock frequency of 166MHz under HL-T

and 200MHz under HS-T. The HYPERBUS™ mode supports DS for capturing data.

4.8.1.2

Read SFDP transaction

The Read Serial Flash Discoverable Parameters (RSFDP_3_0, RDIDSF_1_1) transaction provides access to the

JEDEC Serial Flash Discovery Parameters (SFDP). In SPI mode, the transaction uses a 3-byte address. If a non-zero

address is set, the selected location in the SFDP space is the starting point of the data read. This enables random

access to any parameter in the SFDP space. Read SFDP Transaction is not supported in Read Password mode

before the password is provided. In SPI mode, the maximum clock frequency for the Read SFDP transaction is

156MHz whereas in HYPERBUS™ mode, 166MHz under HL-T, and 200MHz under HS-T. The HYPERBUS™ mode

supports DS for capturing data.

4.8.1.3

Read unique identification transaction

Read Unique Identification (RDUID_0_0, RDIDSF_1_1) transaction is similar to Read Device Identification trans-

action, but accesses a different 64-bit number, which is unique to each device. The Unique ID is factory

programmed.

4.8.1.4

HYPERBUS™ read identification related register and transaction

4.8.1.5

Legacy (x1) SPI read identification related register and transaction

Table 41

HYPERBUS™ read identification related registers and transactions

Related registers

(see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions

(see Table 120 on page 124)

HYPERBUS™ Configuration Register 1 (CFR1N, CFR1V)

Read ID/Unique ID/SFDP (RDIDSF_1_1) - ID/Unique ID/SFDP ASO

Table 42

Legacy (x1) SPI read identification related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

SPI Configuration Register 3 (CFR3N, CFR3V)

Read Identification (RDIDN_0_0)

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