26HS01GTAM03 datasheet(7/166 Pages) INFINEON

7 / 166 page

Datasheet

7 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Pinout and signal description

Table 1

Signal description

Symbol

Type

Mandatory /

optional

Description

CS#

Input

Mandatory

Chip Select (CS#). All bus transactions are initiated with a HIGH to LOW transition on CS#

and terminated with a LOW to HIGH transition on CS#. Driving CS# LOW enables the device,

placing it in the Active mode. When CS# is driven HIGH, the device enters Standby mode,

unless an internal embedded operation is in progress. All other input pins are ignored and

the output pins are put in HIGH impedance state.

CK, CK#[2, 3]

Input

Mandatory

Clock (CK, CK#). Clock provides the timing of the serial interface. Single ended and differ-

ential clock modes are offered. Transactions are latched either on the rising edge of CK

signal (single ended) or on the crossing of the CK and CK# signals (differential).

In Legacy (x1) SPI interface, command, address and data inputs are latched on rising edge

of the clock, and data is output on the falling edge of the clock.

In HYPERBUS™ (x8) interface, for single ended clock, command, address and data input are

latched with respect to the rising and falling edge of the CK. In differential clock mode,

command, address and data inputs are latched with respect to the crossing of CK and CK#.

Differential Clock. CK and CK# are used.

Single Ended: CK is used (CK# is not used and can be left floating).

Output

Mandatory

Read DS. DS is used for data read operations only and indicates output data valid for

HYPERBUS™ interface. During a read transaction while CS# is LOW, DS toggles to

synchronize data output until CS# goes HIGH. Output data during read transactions are

edge aligned with DS.

DQ[7:0]

Input/Output

Mandatory

Serial Data (DQ[7:0]). Bidirectional signals that transfer command, address and data

information.

Legacy (x1) SPI Interface: DQ[0] is an input (SI) and DQ[1] is an output (SO).

HYPERBUS™ (x8) Interface: DQ[7:0] are input and output.

RESET#

Input (weak pull-up)

Optional

Hardware Reset (RESET#). When Low, the device will self initialize and return to the array

read state. DS and DQ[7:0] are placed into the High-Z state when RESET# is Low. RESET#

includes a weak pull-up, meaning, if RESET# is left unconnected it will be pulled up to the

High state.

INT#

Output

(open drain)

Optional

System Interrupt (INT#). When LOW, the device is indicating that an internal event has

occurred. This signal is intended to be used as a system level interrupt for the device to

indicate that an on-chip event has occurred. INT# is an open-drain output.

RSTO#

Output

(open drain)

Optional

Reset Output (RSTO#). RSTO# is an open-drain output used to indicate when a power-on

reset (POR) is occurring within the device and can be used as a system level reset signal.

Upon completion of the internal POR the RSTO# signal will transition from low to high

impedance after a user defined timeout period has elapsed. Upon transition to the high

impedance state the external pull-up resistance will pull RSTO# High and the device

immediately is placed into the Standby state. Transactions are blocked when RSTO# is

LOW. During this period, the device cannot be selected, will not accept any transactions,

and does not drive outputs other than RSTO#.

VCC

Power supply

Mandatory

Core Power Supply

VCCQ

Power supply

Mandatory

Input / Output Power Supply

VSS

Ground supply

Mandatory

Core Ground

VSSQ

Ground supply

Mandatory

Input / Output Ground

DNU

–

Do Not Use.

Notes

2. The clock is not required to be free running.

3. CK and CK# are not true differential signals. They are compliment signals. Care must be taken to ensure system level terminations are properly

designed in.

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