26HS01GTAM03 datasheet(54/166 Pages) INFINEON

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Datasheet

54 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.8.2

Read memory array transactions

Memory array data can be read from the memory starting at any byte boundary. Data bytes are sequentially read

from incrementally higher byte addresses until the host ends the data transfer by driving CS# input HIGH. If the

byte address reaches the maximum address of the memory array, the read will continue at address zero of the

array.

4.8.2.1

Read transaction - HYPERBUS™

The HYPERBUS™ Read transaction provides the fastest data throughput using DDR protocol. This protocol

supports DS for capturing data. The option of linear burst length as well as wrapped burst length is available. This

transaction uses latency cycles set by (CFR1V[7:4]) to enable maximum clock frequency of 166MHz under HL-T,

and 200MHz under HS-T.

4.8.2.2

Read and fast read transactions - Legacy (x1) SPI

The SPI Read and Fast Read transactions are supported for Host systems that require backward compatibility to

legacy SPI. This protocol does not support the DS for capture of data. The options of linear and wrapped read

length is available. The Read transaction supports a maximum clock frequency of 50MHz and requires no latency

cycles. The Fast Read Transaction uses latency cycles set by (CFR2V[3:0]) to enable maximum clock frequency of

166MHz.

4.8.2.3

HYPERBUS™ read memory array related registers and transactions

4.8.2.4

Legacy (x1) SPI read memory array related registers and transactions

4.8.3

Read registers transactions

There are multiple registers for reporting embedded operation status as well as controlling device configuration

options. Registers contain both volatile and nonvolatile bits. There are two transaction types to read the

Registers, namely generic and dedicated. Generic (Read Any Register) transaction provides a way to read all

device registers: Nonvolatile and Volatile by address selection. Dedicated Register Read transactions which is

defined per register and only reads the contents of that register. Legacy (x1) SPI supports both transaction types

whereas HYPERBUS™ supports dedicated transactions only.

4.8.3.1

Read configuration register transaction - HYPERBUS™

The Read Configuration Register (RDVCR1_4_0, RDVCR2_4_0, RDNCR1_4_0, RDNCR2_4_0) transactions read

both the device Configuration registers (Volatile and Nonvolatile). This is followed by a number of latency cycles

set by (CFR1V[7:4]) to enable maximum clock frequency of 166MHz under HL-T HYPERBUS™ mode, and 200MHz

under HS-T. The protocol supports DS for capturing data.

Table 43

HYPERBUS™ read memory array related registers and transactions

Related registers

(see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions

(see Table 120 on page 124)

HYPERBUS™ Configuration Register 1 (CFR2N, CFR2V)

Read (RDMARY_1_0)

Table 44

Legacy (x1) SPI read memory array related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

SPI Configuration Register 2 (CFR2N, CFR2V)

Read (RDAY1_4_0, RDAY1_C_0)

SPI Configuration Register 4 (CFR4N, CFR4V)

Read Fast (RDAY2_C_0)

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