26HS01GTAM03 datasheet(92/166 Pages) INFINEON

92 / 166 page

Datasheet

92 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Registers

5.2.2

Configuration register 2 (CFR2x) (x8)

Configuration Register 2 controls device functionality.

Table 68

HYPERBUS™ maximum operating frequency for MEMLAT[3:0] latency code options

Latency code

Latency clocks initial latency

single/double

Single initial latency

maximum frequency (MHz)

Double initial latency

maximum frequency (MHz)

0000

5/10

107

0001

6/12

121

0010

7/14

135

0011

8/16

100

150

0100

9/18

107

164

0101

10/20

114

178

0110

11/22

128

192

0111

12/24

142

200

1000

13/26

157

200

1001

14/28

171

200

1010

15/30

185

200

1011

16/32

200

1100

20/40

200

1101

Reserved

–

1110

Reserved

–

1111

Reserved

–

Table 69

Configuration register 2 (x8)

Bit number

Name

Function

Read/write

N = Nonvolatile

V = Volatile

Factory

default

(binary)

Description

CFR2V[15:8]

RESVRD

Reserved for Future Use

N => R/W

V => R/W

11111111

These bits are Reserved for future use. This bit must always be

written/loaded to its default state.

CFR2N[7]

CFR2V[7]

PGLTNS

Memory Read Page

Boundary Latency

selection

N => R/W

V => R/W

Description:

The PGLTNS bit selects whether single or double initial

latency is encountered during read instructions. Double

initial latency ensures there is no inter-page boundary

latency.

Selection Options:

0 = Double initial latency - zero latency at page boundaries

1 = Single initial latency - latency at page boundaries

Dependency: N/A

CFR2N[6]

CFR2V[6]

ATP12S

Address Trap Register

1-bit or 1-bit/2-bit ECC

Error selection

N => R/W

V => R/W

Description:

The ATP12S bit selects between 1-bit ECC error

detection/correction or both 1-bit ECC error

detection/correction and 2-bit ECC error detection for

Address Trap Register.

Selection Options:

1 = Address Trap Register traps address of 2-bit ECC errors

0 = Address Trap Register traps address of both 1-bit and 2-bit

ECC errors

Dependency: N/A

CFR2N[5]

CFR2V[5]

ECC12S

Error Correction Code

(ECC) 1-bit or 1-bit/2-bit

error correction

selection

N => R/W

V => R/W

Description:

The ECC12S bit selects between 1-bit ECC error

detection/correction or both 1-bit ECC error detection and

correction and 2-bit ECC error detection.

Selection Options:

0 = 1-bit ECC Error Detection/Correction and 2-bit ECC error

detection

1 = 1-bit ECC Error Detection/Correction

Dependency: N/A

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