26HS01GTAM03 datasheet(8/166 Pages) INFINEON

8 / 166 page

Datasheet

8 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Interface overview

2.1

General description

The CYPRESS™ SEMPER™ Flash family of products are high-speed CMOS, MIRRORBIT™NOR Flash devices that are

compliant with the JEDEC JESD251 eXpanded SPI (xSPI) specification. SEMPER™ Flash is designed for Functional

Safety with development according to ISO 26262 standard to achieve ASIL-B compliance and ASIL-D readiness.

SEMPER™ Flash with HYPERBUS™ interface devices support both the HYPERBUS™ interface as well as legacy (x1)

SPI. Both interfaces serially transfer transactions reducing the number of interface connection signals. SPI

supports SDR whereas HYPERBUS™ supports DDR.

The HYPERBUS™ interface (DDR) transfers two data bytes per clock cycle on the data (DQ) signals. A read or

program/write access consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPER-

FLASH™ core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. Both data

and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals

are used for signal capture by SEMPER™ Flash when receiving command/address/data information on the DQ

signals. The Read DS is an output from SEMPER™ Flash that indicates when data is being transferred from the

memory. DS is referenced to the rising and falling edges of CK during the data transfer portion of read operations.

Command/address/write-data values are center aligned with the clock edges and read-data values are edge

aligned with the transitions of DS.

Read and program/write operations to SEMPER™ Flash are burst oriented. Read transactions can be specified to

use either a wrapped or linear burst. During wrapped operation, accesses start at a selected location and

continue for a configured number of locations in a group wrap sequence. During linear operation accesses start

at a selected location and continue in a sequential manner until the read operation is terminated, when CS#

returns HIGH. Write transactions transfer one or more16-bit values.

Each random read accesses a 32-Byte length and aligned set of data called a page. Each page consists of a pair

of 16-byte aligned groups of array data called half-pages. Half-pages are aligned on 16-byte address boundaries.

A read access requires two clock cycles to define the target half-page address and the burst type, then an

additional initial latency. During the initial latency period the third clock cycle will specify the starting address

within the target half-page. After the initial data value has been output, additional data can be read from the page

on subsequent clock cycles in either a wrapped or linear manner. When configured in linear burst mode, while a

page is being burst out, the device will automatically fetch the next sequential page from the MIRRORBIT™ flash

memory array. This simultaneous burst output while fetching from the array allows for a linear sequential burst

operation that can provide a sustained output of 400/333-MBps data rate [1-Byte (8-bit data bus) * 2 (Data on both

clock edges) * 200/166MHz = 400/333-MBps]

The erased state of each memory bit is a logic 1. Programming changes a logic 1 (HIGH) to a logic 0 (LOW). Only

an erase operation can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete

sector (4KB or 256KB).

SEMPER™ Flash provides a flexible sector architecture. The address space can be configured as either a uniform

256KB sector array, or a hybrid configuration 1 array where thirty-two 4KB sectors are either at the top or at the

bottom while the remaining sectors are all 256KB, or a hybrid configuration 2 array where the thirty-two 4KB

sectors are equally split between the top and the bottom while the remaining sectors are all 256KB.

The page programming buffer used during a single programming operation is configurable to either 256 bytes or

512 bytes. The 512 byte option provides the highest programming throughput.

26HS01GTAM03 数据表(PDF) 8 Page - Infineon Technologies AG

26HS01GTAM03 数据表(HTML) 8 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载