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MPFS160T 数据表(PDF) 18 Page - Microchip Technology |
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MPFS160T 数据表(HTML) 18 Page - Microchip Technology |
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18 / 50 page ![]() Figure 3-2. AXI Switch Connectivity Table 3-4. Processor Interconnect Master PMP Region Count FIC_0 16 FIC_1 16 FIC_2 8 Crytpo 4 Ethernet_0 8 Ethernet_1 8 USB 4 MMC 4 DRI 8 Trace 2 3.5 Processor I/O The PolarFire SoC Microprocessor Subsystem supports 38 general-purpose IOs called as MSS IOs apart from DDR IOs, SGMII IO for Ethernet MACs, and IOs for reference clocks. The MSS IOs support the following peripherals. • eMMC/SD/SDIO • USB • QSPI-XIP • Two CAN • Five UARTs • Two SPI Microprocessor Subsystem © 2021 Microchip Technology Inc. and its subsidiaries Overview DS60001656C-page 18 |
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